769 lines
21 KiB
C
769 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
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*
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* Derived from the ems_pci.c driver:
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* Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
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* Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
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* Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/pci.h>
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#include <linux/can/dev.h>
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#include <linux/io.h>
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#include "sja1000.h"
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#define DRV_NAME "sja1000_plx_pci"
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MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
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MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
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"the SJA1000 chips");
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MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
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"Adlink PCI-7841/cPCI-7841 SE, "
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"Marathon CAN-bus-PCI, "
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"Marathon CAN-bus-PCIe, "
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"TEWS TECHNOLOGIES TPMC810, "
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"esd CAN-PCI/CPCI/PCI104/200, "
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"esd CAN-PCI/PMC/266, "
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"esd CAN-PCIe/2000, "
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"Connect Tech Inc. CANpro/104-Plus Opto (CRG001), "
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"IXXAT PC-I 04/PCI, "
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"ELCUS CAN-200-PCI, "
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"ASEM DUAL CAN-RAW")
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MODULE_LICENSE("GPL v2");
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#define PLX_PCI_MAX_CHAN 2
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struct plx_pci_card {
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int channels; /* detected channels count */
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struct net_device *net_dev[PLX_PCI_MAX_CHAN];
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void __iomem *conf_addr;
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/* Pointer to device-dependent reset function */
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void (*reset_func)(struct pci_dev *pdev);
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};
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#define PLX_PCI_CAN_CLOCK (16000000 / 2)
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/* PLX9030/9050/9052 registers */
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#define PLX_INTCSR 0x4c /* Interrupt Control/Status */
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#define PLX_CNTRL 0x50 /* User I/O, Direct Slave Response,
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* Serial EEPROM, and Initialization
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* Control register
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*/
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#define PLX_LINT1_EN 0x1 /* Local interrupt 1 enable */
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#define PLX_LINT1_POL (1 << 1) /* Local interrupt 1 polarity */
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#define PLX_LINT2_EN (1 << 3) /* Local interrupt 2 enable */
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#define PLX_LINT2_POL (1 << 4) /* Local interrupt 2 polarity */
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#define PLX_PCI_INT_EN (1 << 6) /* PCI Interrupt Enable */
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#define PLX_PCI_RESET (1 << 30) /* PCI Adapter Software Reset */
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/* PLX9056 registers */
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#define PLX9056_INTCSR 0x68 /* Interrupt Control/Status */
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#define PLX9056_CNTRL 0x6c /* Control / Software Reset */
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#define PLX9056_LINTI (1 << 11)
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#define PLX9056_PCI_INT_EN (1 << 8)
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#define PLX9056_PCI_RCR (1 << 29) /* Read Configuration Registers */
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/*
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* The board configuration is probably following:
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* RX1 is connected to ground.
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* TX1 is not connected.
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* CLKO is not connected.
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* Setting the OCR register to 0xDA is a good idea.
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* This means normal output mode, push-pull and the correct polarity.
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*/
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#define PLX_PCI_OCR (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
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/* OCR setting for ASEM Dual CAN raw */
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#define ASEM_PCI_OCR 0xfe
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/*
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* In the CDR register, you should set CBP to 1.
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* You will probably also want to set the clock divider value to 7
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* (meaning direct oscillator output) because the second SJA1000 chip
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* is driven by the first one CLKOUT output.
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*/
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#define PLX_PCI_CDR (CDR_CBP | CDR_CLKOUT_MASK)
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/* SJA1000 Control Register in the BasicCAN Mode */
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#define REG_CR 0x00
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/* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
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#define REG_CR_BASICCAN_INITIAL 0x21
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#define REG_CR_BASICCAN_INITIAL_MASK 0xa1
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#define REG_SR_BASICCAN_INITIAL 0x0c
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#define REG_IR_BASICCAN_INITIAL 0xe0
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/* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
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#define REG_MOD_PELICAN_INITIAL 0x01
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#define REG_SR_PELICAN_INITIAL 0x3c
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#define REG_IR_PELICAN_INITIAL 0x00
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#define ADLINK_PCI_VENDOR_ID 0x144A
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#define ADLINK_PCI_DEVICE_ID 0x7841
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#define ESD_PCI_SUB_SYS_ID_PCI200 0x0004
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#define ESD_PCI_SUB_SYS_ID_PCI266 0x0009
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#define ESD_PCI_SUB_SYS_ID_PMC266 0x000e
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#define ESD_PCI_SUB_SYS_ID_CPCI200 0x010b
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#define ESD_PCI_SUB_SYS_ID_PCIE2000 0x0200
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#define ESD_PCI_SUB_SYS_ID_PCI104200 0x0501
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#define CAN200PCI_DEVICE_ID 0x9030
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#define CAN200PCI_VENDOR_ID 0x10b5
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#define CAN200PCI_SUB_DEVICE_ID 0x0301
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#define CAN200PCI_SUB_VENDOR_ID 0xe1c5
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#define IXXAT_PCI_VENDOR_ID 0x10b5
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#define IXXAT_PCI_DEVICE_ID 0x9050
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#define IXXAT_PCI_SUB_SYS_ID 0x2540
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#define MARATHON_PCI_DEVICE_ID 0x2715
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#define MARATHON_PCIE_DEVICE_ID 0x3432
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#define TEWS_PCI_VENDOR_ID 0x1498
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#define TEWS_PCI_DEVICE_ID_TMPC810 0x032A
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#define CTI_PCI_VENDOR_ID 0x12c4
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#define CTI_PCI_DEVICE_ID_CRG001 0x0900
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#define MOXA_PCI_VENDOR_ID 0x1393
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#define MOXA_PCI_DEVICE_ID 0x0100
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#define ASEM_RAW_CAN_VENDOR_ID 0x10b5
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#define ASEM_RAW_CAN_DEVICE_ID 0x9030
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#define ASEM_RAW_CAN_SUB_VENDOR_ID 0x3000
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#define ASEM_RAW_CAN_SUB_DEVICE_ID 0x1001
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#define ASEM_RAW_CAN_SUB_DEVICE_ID_BIS 0x1002
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#define ASEM_RAW_CAN_RST_REGISTER 0x54
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#define ASEM_RAW_CAN_RST_MASK_CAN1 0x20
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#define ASEM_RAW_CAN_RST_MASK_CAN2 0x04
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static void plx_pci_reset_common(struct pci_dev *pdev);
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static void plx9056_pci_reset_common(struct pci_dev *pdev);
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static void plx_pci_reset_marathon_pci(struct pci_dev *pdev);
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static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev);
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static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev);
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struct plx_pci_channel_map {
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u32 bar;
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u32 offset;
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u32 size; /* 0x00 - auto, e.g. length of entire bar */
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};
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struct plx_pci_card_info {
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const char *name;
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int channel_count;
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u32 can_clock;
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u8 ocr; /* output control register */
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u8 cdr; /* clock divider register */
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/* Parameters for mapping local configuration space */
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struct plx_pci_channel_map conf_map;
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/* Parameters for mapping the SJA1000 chips */
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struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
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/* Pointer to device-dependent reset function */
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void (*reset_func)(struct pci_dev *pdev);
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};
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static struct plx_pci_card_info plx_pci_card_info_adlink = {
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"Adlink PCI-7841/cPCI-7841", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
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&plx_pci_reset_common
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/* based on PLX9052 */
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};
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static struct plx_pci_card_info plx_pci_card_info_adlink_se = {
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"Adlink PCI-7841/cPCI-7841 SE", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
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&plx_pci_reset_common
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/* based on PLX9052 */
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};
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static struct plx_pci_card_info plx_pci_card_info_esd200 = {
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"esd CAN-PCI/CPCI/PCI104/200", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
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&plx_pci_reset_common
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/* based on PLX9030/9050 */
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};
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static struct plx_pci_card_info plx_pci_card_info_esd266 = {
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"esd CAN-PCI/PMC/266", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
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&plx9056_pci_reset_common
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/* based on PLX9056 */
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};
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static struct plx_pci_card_info plx_pci_card_info_esd2000 = {
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"esd CAN-PCIe/2000", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x100, 0x80} },
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&plx9056_pci_reset_common
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/* based on PEX8311 */
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};
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static struct plx_pci_card_info plx_pci_card_info_ixxat = {
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"IXXAT PC-I 04/PCI", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x200, 0x80} },
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&plx_pci_reset_common
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/* based on PLX9050 */
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};
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static struct plx_pci_card_info plx_pci_card_info_marathon_pci = {
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"Marathon CAN-bus-PCI", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
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&plx_pci_reset_marathon_pci
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/* based on PLX9052 */
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};
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static struct plx_pci_card_info plx_pci_card_info_marathon_pcie = {
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"Marathon CAN-bus-PCIe", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x00, 0x00}, {3, 0x80, 0x00} },
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&plx_pci_reset_marathon_pcie
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/* based on PEX8311 */
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};
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static struct plx_pci_card_info plx_pci_card_info_tews = {
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"TEWS TECHNOLOGIES TPMC810", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
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&plx_pci_reset_common
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/* based on PLX9030 */
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};
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static struct plx_pci_card_info plx_pci_card_info_cti = {
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"Connect Tech Inc. CANpro/104-Plus Opto (CRG001)", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
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&plx_pci_reset_common
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/* based on PLX9030 */
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};
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static struct plx_pci_card_info plx_pci_card_info_elcus = {
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"Eclus CAN-200-PCI", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{1, 0x00, 0x00}, { {2, 0x00, 0x80}, {3, 0x00, 0x80} },
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&plx_pci_reset_common
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/* based on PLX9030 */
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};
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static struct plx_pci_card_info plx_pci_card_info_moxa = {
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"MOXA", 2,
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PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {0, 0x00, 0x80}, {1, 0x00, 0x80} },
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&plx_pci_reset_common
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/* based on PLX9052 */
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};
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static struct plx_pci_card_info plx_pci_card_info_asem_dual_can = {
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"ASEM Dual CAN raw PCI", 2,
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PLX_PCI_CAN_CLOCK, ASEM_PCI_OCR, PLX_PCI_CDR,
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{0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
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&plx_pci_reset_asem_dual_can_raw
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/* based on PLX9030 */
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};
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static const struct pci_device_id plx_pci_tbl[] = {
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{
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/* Adlink PCI-7841/cPCI-7841 */
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ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
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PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_NETWORK_OTHER << 8, ~0,
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(kernel_ulong_t)&plx_pci_card_info_adlink
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},
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{
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/* Adlink PCI-7841/cPCI-7841 SE */
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ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
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PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
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(kernel_ulong_t)&plx_pci_card_info_adlink_se
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},
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{
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/* esd CAN-PCI/200 */
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PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
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PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI200,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_esd200
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},
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{
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/* esd CAN-CPCI/200 */
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PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
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PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_CPCI200,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_esd200
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},
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{
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/* esd CAN-PCI104/200 */
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PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
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PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI104200,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_esd200
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},
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{
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/* esd CAN-PCI/266 */
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PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
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PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCI266,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_esd266
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},
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{
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/* esd CAN-PMC/266 */
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PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
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PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PMC266,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_esd266
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},
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{
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/* esd CAN-PCIE/2000 */
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PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9056,
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PCI_VENDOR_ID_ESDGMBH, ESD_PCI_SUB_SYS_ID_PCIE2000,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_esd2000
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},
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{
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/* IXXAT PC-I 04/PCI card */
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IXXAT_PCI_VENDOR_ID, IXXAT_PCI_DEVICE_ID,
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PCI_ANY_ID, IXXAT_PCI_SUB_SYS_ID,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_ixxat
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},
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{
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/* Marathon CAN-bus-PCI card */
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PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
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PCI_ANY_ID, PCI_ANY_ID,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_marathon_pci
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},
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{
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/* Marathon CAN-bus-PCIe card */
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PCI_VENDOR_ID_PLX, MARATHON_PCIE_DEVICE_ID,
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PCI_ANY_ID, PCI_ANY_ID,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_marathon_pcie
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},
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{
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/* TEWS TECHNOLOGIES TPMC810 card */
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TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
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PCI_ANY_ID, PCI_ANY_ID,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_tews
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},
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{
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/* Connect Tech Inc. CANpro/104-Plus Opto (CRG001) card */
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PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
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CTI_PCI_VENDOR_ID, CTI_PCI_DEVICE_ID_CRG001,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_cti
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},
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{
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/* Elcus CAN-200-PCI */
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CAN200PCI_VENDOR_ID, CAN200PCI_DEVICE_ID,
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CAN200PCI_SUB_VENDOR_ID, CAN200PCI_SUB_DEVICE_ID,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_elcus
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},
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{
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/* moxa */
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MOXA_PCI_VENDOR_ID, MOXA_PCI_DEVICE_ID,
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PCI_ANY_ID, PCI_ANY_ID,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_moxa
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},
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{
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/* ASEM Dual CAN raw */
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ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
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ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_asem_dual_can
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},
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{
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/* ASEM Dual CAN raw -new model */
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ASEM_RAW_CAN_VENDOR_ID, ASEM_RAW_CAN_DEVICE_ID,
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ASEM_RAW_CAN_SUB_VENDOR_ID, ASEM_RAW_CAN_SUB_DEVICE_ID_BIS,
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0, 0,
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(kernel_ulong_t)&plx_pci_card_info_asem_dual_can
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},
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{ 0,}
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};
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MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
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static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
|
|
{
|
|
return ioread8(priv->reg_base + port);
|
|
}
|
|
|
|
static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
|
|
{
|
|
iowrite8(val, priv->reg_base + port);
|
|
}
|
|
|
|
/*
|
|
* Check if a CAN controller is present at the specified location
|
|
* by trying to switch 'em from the Basic mode into the PeliCAN mode.
|
|
* Also check states of some registers in reset mode.
|
|
*/
|
|
static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
|
|
{
|
|
int flag = 0;
|
|
|
|
/*
|
|
* Check registers after hardware reset (the Basic mode)
|
|
* See states on p. 10 of the Datasheet.
|
|
*/
|
|
if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
|
|
REG_CR_BASICCAN_INITIAL &&
|
|
(priv->read_reg(priv, SJA1000_SR) == REG_SR_BASICCAN_INITIAL) &&
|
|
(priv->read_reg(priv, SJA1000_IR) == REG_IR_BASICCAN_INITIAL))
|
|
flag = 1;
|
|
|
|
/* Bring the SJA1000 into the PeliCAN mode*/
|
|
priv->write_reg(priv, SJA1000_CDR, CDR_PELICAN);
|
|
|
|
/*
|
|
* Check registers after reset in the PeliCAN mode.
|
|
* See states on p. 23 of the Datasheet.
|
|
*/
|
|
if (priv->read_reg(priv, SJA1000_MOD) == REG_MOD_PELICAN_INITIAL &&
|
|
priv->read_reg(priv, SJA1000_SR) == REG_SR_PELICAN_INITIAL &&
|
|
priv->read_reg(priv, SJA1000_IR) == REG_IR_PELICAN_INITIAL)
|
|
return flag;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* PLX9030/50/52 software reset
|
|
* Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
|
|
* For most cards it's enough for reset the SJA1000 chips.
|
|
*/
|
|
static void plx_pci_reset_common(struct pci_dev *pdev)
|
|
{
|
|
struct plx_pci_card *card = pci_get_drvdata(pdev);
|
|
u32 cntrl;
|
|
|
|
cntrl = ioread32(card->conf_addr + PLX_CNTRL);
|
|
cntrl |= PLX_PCI_RESET;
|
|
iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
|
|
udelay(100);
|
|
cntrl ^= PLX_PCI_RESET;
|
|
iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
|
|
};
|
|
|
|
/*
|
|
* PLX9056 software reset
|
|
* Assert LRESET# and reset device(s) on the Local Bus (if wired).
|
|
*/
|
|
static void plx9056_pci_reset_common(struct pci_dev *pdev)
|
|
{
|
|
struct plx_pci_card *card = pci_get_drvdata(pdev);
|
|
u32 cntrl;
|
|
|
|
/* issue a local bus reset */
|
|
cntrl = ioread32(card->conf_addr + PLX9056_CNTRL);
|
|
cntrl |= PLX_PCI_RESET;
|
|
iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
|
|
udelay(100);
|
|
cntrl ^= PLX_PCI_RESET;
|
|
iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
|
|
|
|
/* reload local configuration from EEPROM */
|
|
cntrl |= PLX9056_PCI_RCR;
|
|
iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
|
|
|
|
/*
|
|
* There is no safe way to poll for the end
|
|
* of reconfiguration process. Waiting for 10ms
|
|
* is safe.
|
|
*/
|
|
mdelay(10);
|
|
|
|
cntrl ^= PLX9056_PCI_RCR;
|
|
iowrite32(cntrl, card->conf_addr + PLX9056_CNTRL);
|
|
};
|
|
|
|
/* Special reset function for Marathon CAN-bus-PCI card */
|
|
static void plx_pci_reset_marathon_pci(struct pci_dev *pdev)
|
|
{
|
|
void __iomem *reset_addr;
|
|
int i;
|
|
static const int reset_bar[2] = {3, 5};
|
|
|
|
plx_pci_reset_common(pdev);
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
reset_addr = pci_iomap(pdev, reset_bar[i], 0);
|
|
if (!reset_addr) {
|
|
dev_err(&pdev->dev, "Failed to remap reset "
|
|
"space %d (BAR%d)\n", i, reset_bar[i]);
|
|
} else {
|
|
/* reset the SJA1000 chip */
|
|
iowrite8(0x1, reset_addr);
|
|
udelay(100);
|
|
pci_iounmap(pdev, reset_addr);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Special reset function for Marathon CAN-bus-PCIe card */
|
|
static void plx_pci_reset_marathon_pcie(struct pci_dev *pdev)
|
|
{
|
|
void __iomem *addr;
|
|
void __iomem *reset_addr;
|
|
int i;
|
|
|
|
plx9056_pci_reset_common(pdev);
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
struct plx_pci_channel_map *chan_map =
|
|
&plx_pci_card_info_marathon_pcie.chan_map_tbl[i];
|
|
addr = pci_iomap(pdev, chan_map->bar, chan_map->size);
|
|
if (!addr) {
|
|
dev_err(&pdev->dev, "Failed to remap reset "
|
|
"space %d (BAR%d)\n", i, chan_map->bar);
|
|
} else {
|
|
/* reset the SJA1000 chip */
|
|
#define MARATHON_PCIE_RESET_OFFSET 32
|
|
reset_addr = addr + chan_map->offset +
|
|
MARATHON_PCIE_RESET_OFFSET;
|
|
iowrite8(0x1, reset_addr);
|
|
udelay(100);
|
|
pci_iounmap(pdev, addr);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Special reset function for ASEM Dual CAN raw card */
|
|
static void plx_pci_reset_asem_dual_can_raw(struct pci_dev *pdev)
|
|
{
|
|
void __iomem *bar0_addr;
|
|
u8 tmpval;
|
|
|
|
plx_pci_reset_common(pdev);
|
|
|
|
bar0_addr = pci_iomap(pdev, 0, 0);
|
|
if (!bar0_addr) {
|
|
dev_err(&pdev->dev, "Failed to remap reset space 0 (BAR0)\n");
|
|
return;
|
|
}
|
|
|
|
/* reset the two SJA1000 chips */
|
|
tmpval = ioread8(bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
|
|
tmpval &= ~(ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2);
|
|
iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
|
|
usleep_range(300, 400);
|
|
tmpval |= ASEM_RAW_CAN_RST_MASK_CAN1 | ASEM_RAW_CAN_RST_MASK_CAN2;
|
|
iowrite8(tmpval, bar0_addr + ASEM_RAW_CAN_RST_REGISTER);
|
|
usleep_range(300, 400);
|
|
pci_iounmap(pdev, bar0_addr);
|
|
}
|
|
|
|
static void plx_pci_del_card(struct pci_dev *pdev)
|
|
{
|
|
struct plx_pci_card *card = pci_get_drvdata(pdev);
|
|
struct net_device *dev;
|
|
struct sja1000_priv *priv;
|
|
int i = 0;
|
|
|
|
for (i = 0; i < PLX_PCI_MAX_CHAN; i++) {
|
|
dev = card->net_dev[i];
|
|
if (!dev)
|
|
continue;
|
|
|
|
dev_info(&pdev->dev, "Removing %s\n", dev->name);
|
|
unregister_sja1000dev(dev);
|
|
priv = netdev_priv(dev);
|
|
if (priv->reg_base)
|
|
pci_iounmap(pdev, priv->reg_base);
|
|
free_sja1000dev(dev);
|
|
}
|
|
|
|
card->reset_func(pdev);
|
|
|
|
/*
|
|
* Disable interrupts from PCI-card and disable local
|
|
* interrupts
|
|
*/
|
|
if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
|
|
pdev->device != MARATHON_PCIE_DEVICE_ID)
|
|
iowrite32(0x0, card->conf_addr + PLX_INTCSR);
|
|
else
|
|
iowrite32(0x0, card->conf_addr + PLX9056_INTCSR);
|
|
|
|
if (card->conf_addr)
|
|
pci_iounmap(pdev, card->conf_addr);
|
|
|
|
kfree(card);
|
|
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
/*
|
|
* Probe PLX90xx based device for the SJA1000 chips and register each
|
|
* available CAN channel to SJA1000 Socket-CAN subsystem.
|
|
*/
|
|
static int plx_pci_add_card(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
struct sja1000_priv *priv;
|
|
struct net_device *dev;
|
|
struct plx_pci_card *card;
|
|
struct plx_pci_card_info *ci;
|
|
int err, i;
|
|
u32 val;
|
|
void __iomem *addr;
|
|
|
|
ci = (struct plx_pci_card_info *)ent->driver_data;
|
|
|
|
if (pci_enable_device(pdev) < 0) {
|
|
dev_err(&pdev->dev, "Failed to enable PCI device\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
|
|
ci->name, PCI_SLOT(pdev->devfn));
|
|
|
|
/* Allocate card structures to hold addresses, ... */
|
|
card = kzalloc(sizeof(*card), GFP_KERNEL);
|
|
if (!card) {
|
|
pci_disable_device(pdev);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
pci_set_drvdata(pdev, card);
|
|
|
|
card->channels = 0;
|
|
|
|
/* Remap PLX90xx configuration space */
|
|
addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
|
|
if (!addr) {
|
|
err = -ENOMEM;
|
|
dev_err(&pdev->dev, "Failed to remap configuration space "
|
|
"(BAR%d)\n", ci->conf_map.bar);
|
|
goto failure_cleanup;
|
|
}
|
|
card->conf_addr = addr + ci->conf_map.offset;
|
|
|
|
ci->reset_func(pdev);
|
|
card->reset_func = ci->reset_func;
|
|
|
|
/* Detect available channels */
|
|
for (i = 0; i < ci->channel_count; i++) {
|
|
struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
|
|
|
|
dev = alloc_sja1000dev(0);
|
|
if (!dev) {
|
|
err = -ENOMEM;
|
|
goto failure_cleanup;
|
|
}
|
|
|
|
card->net_dev[i] = dev;
|
|
priv = netdev_priv(dev);
|
|
priv->priv = card;
|
|
priv->irq_flags = IRQF_SHARED;
|
|
|
|
dev->irq = pdev->irq;
|
|
|
|
/*
|
|
* Remap IO space of the SJA1000 chips
|
|
* This is device-dependent mapping
|
|
*/
|
|
addr = pci_iomap(pdev, cm->bar, cm->size);
|
|
if (!addr) {
|
|
err = -ENOMEM;
|
|
dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
|
|
goto failure_cleanup;
|
|
}
|
|
|
|
priv->reg_base = addr + cm->offset;
|
|
priv->read_reg = plx_pci_read_reg;
|
|
priv->write_reg = plx_pci_write_reg;
|
|
|
|
/* Check if channel is present */
|
|
if (plx_pci_check_sja1000(priv)) {
|
|
priv->can.clock.freq = ci->can_clock;
|
|
priv->ocr = ci->ocr;
|
|
priv->cdr = ci->cdr;
|
|
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
dev->dev_id = i;
|
|
|
|
/* Register SJA1000 device */
|
|
err = register_sja1000dev(dev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "Registering device failed "
|
|
"(err=%d)\n", err);
|
|
goto failure_cleanup;
|
|
}
|
|
|
|
card->channels++;
|
|
|
|
dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
|
|
"registered as %s\n", i + 1, priv->reg_base,
|
|
dev->irq, dev->name);
|
|
} else {
|
|
dev_err(&pdev->dev, "Channel #%d not detected\n",
|
|
i + 1);
|
|
free_sja1000dev(dev);
|
|
card->net_dev[i] = NULL;
|
|
}
|
|
}
|
|
|
|
if (!card->channels) {
|
|
err = -ENODEV;
|
|
goto failure_cleanup;
|
|
}
|
|
|
|
/*
|
|
* Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
|
|
* Local_2 interrupts from the SJA1000 chips
|
|
*/
|
|
if (pdev->device != PCI_DEVICE_ID_PLX_9056 &&
|
|
pdev->device != MARATHON_PCIE_DEVICE_ID) {
|
|
val = ioread32(card->conf_addr + PLX_INTCSR);
|
|
if (pdev->subsystem_vendor == PCI_VENDOR_ID_ESDGMBH)
|
|
val |= PLX_LINT1_EN | PLX_PCI_INT_EN;
|
|
else
|
|
val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
|
|
iowrite32(val, card->conf_addr + PLX_INTCSR);
|
|
} else {
|
|
iowrite32(PLX9056_LINTI | PLX9056_PCI_INT_EN,
|
|
card->conf_addr + PLX9056_INTCSR);
|
|
}
|
|
return 0;
|
|
|
|
failure_cleanup:
|
|
dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
|
|
|
|
plx_pci_del_card(pdev);
|
|
|
|
return err;
|
|
}
|
|
|
|
static struct pci_driver plx_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = plx_pci_tbl,
|
|
.probe = plx_pci_add_card,
|
|
.remove = plx_pci_del_card,
|
|
};
|
|
|
|
module_pci_driver(plx_pci_driver);
|