309 lines
7.4 KiB
C
309 lines
7.4 KiB
C
/*
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* Common pmac/prep/chrp pci routines. -- Cort
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/capability.h>
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/list.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/sections.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#include <asm/byteorder.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#undef DEBUG
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unsigned long isa_io_base = 0;
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unsigned long pci_dram_offset = 0;
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int pcibios_assign_bus_offset = 1;
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void pcibios_make_OF_bus_map(void);
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static void fixup_cpc710_pci64(struct pci_dev* dev);
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static u8* pci_to_OF_bus_map;
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/* By default, we don't re-assign bus numbers. We do this only on
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* some pmacs
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*/
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static int pci_assign_all_buses;
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static int pci_bus_count;
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/* This will remain NULL for now, until isa-bridge.c is made common
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* to both 32-bit and 64-bit.
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*/
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struct pci_dev *isa_bridge_pcidev;
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EXPORT_SYMBOL_GPL(isa_bridge_pcidev);
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static void
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fixup_cpc710_pci64(struct pci_dev* dev)
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{
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/* Hide the PCI64 BARs from the kernel as their content doesn't
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* fit well in the resource management
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*/
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dev->resource[0].start = dev->resource[0].end = 0;
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dev->resource[0].flags = 0;
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dev->resource[1].start = dev->resource[1].end = 0;
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dev->resource[1].flags = 0;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CPC710_PCI64, fixup_cpc710_pci64);
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/*
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* Functions below are used on OpenFirmware machines.
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*/
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static void
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make_one_node_map(struct device_node* node, u8 pci_bus)
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{
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const int *bus_range;
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int len;
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if (pci_bus >= pci_bus_count)
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return;
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bus_range = of_get_property(node, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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printk(KERN_WARNING "Can't get bus-range for %s, "
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"assuming it starts at 0\n", node->full_name);
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pci_to_OF_bus_map[pci_bus] = 0;
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} else
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pci_to_OF_bus_map[pci_bus] = bus_range[0];
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for_each_child_of_node(node, node) {
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struct pci_dev* dev;
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const unsigned int *class_code, *reg;
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class_code = of_get_property(node, "class-code", NULL);
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if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
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(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
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continue;
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reg = of_get_property(node, "reg", NULL);
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if (!reg)
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continue;
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dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
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if (!dev || !dev->subordinate) {
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pci_dev_put(dev);
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continue;
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}
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make_one_node_map(node, dev->subordinate->number);
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pci_dev_put(dev);
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}
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}
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void
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pcibios_make_OF_bus_map(void)
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{
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int i;
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struct pci_controller *hose, *tmp;
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struct property *map_prop;
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struct device_node *dn;
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pci_to_OF_bus_map = kmalloc(pci_bus_count, GFP_KERNEL);
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if (!pci_to_OF_bus_map) {
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printk(KERN_ERR "Can't allocate OF bus map !\n");
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return;
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}
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/* We fill the bus map with invalid values, that helps
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* debugging.
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*/
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for (i=0; i<pci_bus_count; i++)
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pci_to_OF_bus_map[i] = 0xff;
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/* For each hose, we begin searching bridges */
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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struct device_node* node = hose->dn;
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if (!node)
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continue;
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make_one_node_map(node, hose->first_busno);
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}
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dn = of_find_node_by_path("/");
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map_prop = of_find_property(dn, "pci-OF-bus-map", NULL);
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if (map_prop) {
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BUG_ON(pci_bus_count > map_prop->length);
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memcpy(map_prop->value, pci_to_OF_bus_map, pci_bus_count);
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}
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of_node_put(dn);
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#ifdef DEBUG
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printk("PCI->OF bus map:\n");
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for (i=0; i<pci_bus_count; i++) {
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if (pci_to_OF_bus_map[i] == 0xff)
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continue;
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printk("%d -> %d\n", i, pci_to_OF_bus_map[i]);
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}
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#endif
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}
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/*
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* Returns the PCI device matching a given OF node
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*/
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int pci_device_from_OF_node(struct device_node *node, u8 *bus, u8 *devfn)
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{
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struct pci_dev *dev = NULL;
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const __be32 *reg;
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int size;
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/* Check if it might have a chance to be a PCI device */
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if (!pci_find_hose_for_OF_device(node))
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return -ENODEV;
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reg = of_get_property(node, "reg", &size);
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if (!reg || size < 5 * sizeof(u32))
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return -ENODEV;
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*bus = (be32_to_cpup(®[0]) >> 16) & 0xff;
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*devfn = (be32_to_cpup(®[0]) >> 8) & 0xff;
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/* Ok, here we need some tweak. If we have already renumbered
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* all busses, we can't rely on the OF bus number any more.
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* the pci_to_OF_bus_map is not enough as several PCI busses
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* may match the same OF bus number.
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*/
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if (!pci_to_OF_bus_map)
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return 0;
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for_each_pci_dev(dev)
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if (pci_to_OF_bus_map[dev->bus->number] == *bus &&
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dev->devfn == *devfn) {
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*bus = dev->bus->number;
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pci_dev_put(dev);
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return 0;
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}
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return -ENODEV;
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}
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EXPORT_SYMBOL(pci_device_from_OF_node);
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/* We create the "pci-OF-bus-map" property now so it appears in the
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* /proc device tree
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*/
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void __init
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pci_create_OF_bus_map(void)
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{
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struct property* of_prop;
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struct device_node *dn;
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of_prop = memblock_virt_alloc(sizeof(struct property) + 256, 0);
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dn = of_find_node_by_path("/");
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if (dn) {
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memset(of_prop, -1, sizeof(struct property) + 256);
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of_prop->name = "pci-OF-bus-map";
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of_prop->length = 256;
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of_prop->value = &of_prop[1];
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of_add_property(dn, of_prop);
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of_node_put(dn);
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}
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}
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void pcibios_setup_phb_io_space(struct pci_controller *hose)
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{
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unsigned long io_offset;
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struct resource *res = &hose->io_resource;
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/* Fixup IO space offset */
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io_offset = pcibios_io_space_offset(hose);
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res->start += io_offset;
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res->end += io_offset;
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}
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose, *tmp;
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int next_busno = 0;
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printk(KERN_INFO "PCI: Probing PCI hardware\n");
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if (pci_has_flag(PCI_REASSIGN_ALL_BUS))
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pci_assign_all_buses = 1;
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/* Scan all of the recorded PCI controllers. */
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
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if (pci_assign_all_buses)
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hose->first_busno = next_busno;
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hose->last_busno = 0xff;
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pcibios_scan_phb(hose);
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pci_bus_add_devices(hose->bus);
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if (pci_assign_all_buses || next_busno <= hose->last_busno)
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next_busno = hose->last_busno + pcibios_assign_bus_offset;
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}
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pci_bus_count = next_busno;
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/* OpenFirmware based machines need a map of OF bus
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* numbers vs. kernel bus numbers since we may have to
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* remap them.
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*/
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if (pci_assign_all_buses)
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pcibios_make_OF_bus_map();
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/* Call common code to handle resource allocation */
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pcibios_resource_survey();
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/* Call machine dependent post-init code */
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if (ppc_md.pcibios_after_init)
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ppc_md.pcibios_after_init();
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return 0;
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}
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subsys_initcall(pcibios_init);
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static struct pci_controller*
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pci_bus_to_hose(int bus)
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{
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struct pci_controller *hose, *tmp;
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
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if (bus >= hose->first_busno && bus <= hose->last_busno)
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return hose;
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return NULL;
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}
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/* Provide information on locations of various I/O regions in physical
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* memory. Do this on a per-card basis so that we choose the right
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* root bridge.
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* Note that the returned IO or memory base is a physical address
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*/
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long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
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{
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struct pci_controller* hose;
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long result = -EOPNOTSUPP;
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hose = pci_bus_to_hose(bus);
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if (!hose)
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return -ENODEV;
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switch (which) {
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case IOBASE_BRIDGE_NUMBER:
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return (long)hose->first_busno;
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case IOBASE_MEMORY:
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return (long)hose->mem_offset[0];
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case IOBASE_IO:
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return (long)hose->io_base_phys;
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case IOBASE_ISA_IO:
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return (long)isa_io_base;
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case IOBASE_ISA_MEM:
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return (long)isa_mem_base;
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}
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return result;
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}
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