144 lines
5.5 KiB
Plaintext
144 lines
5.5 KiB
Plaintext
STMicroelectronics 10/100/1000 Synopsys Ethernet driver
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Copyright (C) 2007-2010 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
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(Synopsys IP blocks); it has been fully tested on STLinux platforms.
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Currently this network device driver is for all STM embedded MAC/GMAC
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(7xxx SoCs).
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DWC Ether MAC 10/100/1000 Universal version 3.41a and DWC Ether MAC 10/100
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Universal version 4.0 have been used for developing the first code
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implementation.
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Please, for more information also visit: www.stlinux.com
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1) Kernel Configuration
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The kernel configuration option is STMMAC_ETH:
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Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) --->
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STMicroelectronics 10/100/1000 Ethernet driver (STMMAC_ETH)
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2) Driver parameters list:
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debug: message level (0: no output, 16: all);
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phyaddr: to manually provide the physical address to the PHY device;
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dma_rxsize: DMA rx ring size;
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dma_txsize: DMA tx ring size;
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buf_sz: DMA buffer size;
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tc: control the HW FIFO threshold;
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tx_coe: Enable/Disable Tx Checksum Offload engine;
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watchdog: transmit timeout (in milliseconds);
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flow_ctrl: Flow control ability [on/off];
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pause: Flow Control Pause Time;
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tmrate: timer period (only if timer optimisation is configured).
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3) Command line options
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Driver parameters can be also passed in command line by using:
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stmmaceth=dma_rxsize:128,dma_txsize:512
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4) Driver information and notes
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4.1) Transmit process
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The xmit method is invoked when the kernel needs to transmit a packet; it sets
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the descriptors in the ring and informs the DMA engine that there is a packet
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ready to be transmitted.
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Once the controller has finished transmitting the packet, an interrupt is
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triggered; So the driver will be able to release the socket buffers.
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By default, the driver sets the NETIF_F_SG bit in the features field of the
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net_device structure enabling the scatter/gather feature.
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4.2) Receive process
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When one or more packets are received, an interrupt happens. The interrupts
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are not queued so the driver has to scan all the descriptors in the ring during
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the receive process.
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This is based on NAPI so the interrupt handler signals only if there is work to be
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done, and it exits.
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Then the poll method will be scheduled at some future point.
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The incoming packets are stored, by the DMA, in a list of pre-allocated socket
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buffers in order to avoid the memcpy (Zero-copy).
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4.3) Timer-Driver Interrupt
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Instead of having the device that asynchronously notifies the frame receptions, the
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driver configures a timer to generate an interrupt at regular intervals.
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Based on the granularity of the timer, the frames that are received by the device
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will experience different levels of latency. Some NICs have dedicated timer
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device to perform this task. STMMAC can use either the RTC device or the TMU
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channel 2 on STLinux platforms.
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The timers frequency can be passed to the driver as parameter; when change it,
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take care of both hardware capability and network stability/performance impact.
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Several performance tests on STM platforms showed this optimisation allows to spare
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the CPU while having the maximum throughput.
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4.4) WOL
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Wake up on Lan feature through Magic Frame is only supported for the GMAC
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core.
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4.5) DMA descriptors
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Driver handles both normal and enhanced descriptors. The latter has been only
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tested on DWC Ether MAC 10/100/1000 Universal version 3.41a.
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4.6) Ethtool support
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Ethtool is supported. Driver statistics and internal errors can be taken using:
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ethtool -S ethX command. It is possible to dump registers etc.
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4.7) Jumbo and Segmentation Offloading
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Jumbo frames are supported and tested for the GMAC.
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The GSO has been also added but it's performed in software.
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LRO is not supported.
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4.8) Physical
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The driver is compatible with PAL to work with PHY and GPHY devices.
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4.9) Platform information
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Several information came from the platform; please refer to the
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driver's Header file in include/linux directory.
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struct plat_stmmacenet_data {
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int bus_id;
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int pbl;
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int has_gmac;
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void (*fix_mac_speed)(void *priv, unsigned int speed);
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void (*bus_setup)(unsigned long ioaddr);
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#ifdef CONFIG_STM_DRIVERS
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struct stm_pad_config *pad_config;
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#endif
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void *bsp_priv;
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};
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Where:
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- pbl (Programmable Burst Length) is maximum number of
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beats to be transferred in one DMA transaction.
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GMAC also enables the 4xPBL by default.
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- fix_mac_speed and bus_setup are used to configure internal target
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registers (on STM platforms);
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- has_gmac: GMAC core is on board (get it at run-time in the next step);
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- bus_id: bus identifier.
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struct plat_stmmacphy_data {
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int bus_id;
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int phy_addr;
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unsigned int phy_mask;
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int interface;
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int (*phy_reset)(void *priv);
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void *priv;
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};
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Where:
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- bus_id: bus identifier;
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- phy_addr: physical address used for the attached phy device;
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set it to -1 to get it at run-time;
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- interface: physical MII interface mode;
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- phy_reset: hook to reset HW function.
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TODO:
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- Continue to make the driver more generic and suitable for other Synopsys
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Ethernet controllers used on other architectures (i.e. ARM).
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- 10G controllers are not supported.
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- MAC uses Normal descriptors and GMAC uses enhanced ones.
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This is a limit that should be reviewed. MAC could want to
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use the enhanced structure.
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- Checksumming: Rx/Tx csum is done in HW in case of GMAC only.
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- Review the timer optimisation code to use an embedded device that seems to be
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available in new chip generations.
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