309 lines
7.6 KiB
C
309 lines
7.6 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "amdgpu.h"
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#include "amdgpu_ih.h"
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#include "sid.h"
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#include "si_ih.h"
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static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
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static void si_ih_enable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_cntl = RREG32(IH_CNTL);
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u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
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ih_cntl |= ENABLE_INTR;
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ih_rb_cntl |= IH_RB_ENABLE;
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WREG32(IH_CNTL, ih_cntl);
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WREG32(IH_RB_CNTL, ih_rb_cntl);
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adev->irq.ih.enabled = true;
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}
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static void si_ih_disable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
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u32 ih_cntl = RREG32(IH_CNTL);
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ih_rb_cntl &= ~IH_RB_ENABLE;
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ih_cntl &= ~ENABLE_INTR;
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WREG32(IH_RB_CNTL, ih_rb_cntl);
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WREG32(IH_CNTL, ih_cntl);
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WREG32(IH_RB_RPTR, 0);
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WREG32(IH_RB_WPTR, 0);
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adev->irq.ih.enabled = false;
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adev->irq.ih.rptr = 0;
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}
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static int si_ih_irq_init(struct amdgpu_device *adev)
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{
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int rb_bufsz;
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u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
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u64 wptr_off;
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si_ih_disable_interrupts(adev);
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WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
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interrupt_cntl = RREG32(INTERRUPT_CNTL);
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interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
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interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
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WREG32(INTERRUPT_CNTL, interrupt_cntl);
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WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
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rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
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ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE |
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IH_WPTR_OVERFLOW_CLEAR |
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(rb_bufsz << 1) |
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IH_WPTR_WRITEBACK_ENABLE;
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wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
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WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
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WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
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WREG32(IH_RB_CNTL, ih_rb_cntl);
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WREG32(IH_RB_RPTR, 0);
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WREG32(IH_RB_WPTR, 0);
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ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
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if (adev->irq.msi_enabled)
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ih_cntl |= RPTR_REARM;
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WREG32(IH_CNTL, ih_cntl);
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pci_set_master(adev->pdev);
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si_ih_enable_interrupts(adev);
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return 0;
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}
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static void si_ih_irq_disable(struct amdgpu_device *adev)
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{
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si_ih_disable_interrupts(adev);
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mdelay(1);
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}
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static u32 si_ih_get_wptr(struct amdgpu_device *adev)
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{
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u32 wptr, tmp;
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wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
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if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
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wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
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dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
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adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
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tmp = RREG32(IH_RB_CNTL);
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tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
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WREG32(IH_RB_CNTL, tmp);
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}
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return (wptr & adev->irq.ih.ptr_mask);
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}
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static void si_ih_decode_iv(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry)
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{
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u32 ring_index = adev->irq.ih.rptr >> 2;
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uint32_t dw[4];
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dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
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dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
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dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
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dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
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entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
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entry->src_id = dw[0] & 0xff;
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entry->src_data[0] = dw[1] & 0xfffffff;
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entry->ring_id = dw[2] & 0xff;
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entry->vm_id = (dw[2] >> 8) & 0xff;
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adev->irq.ih.rptr += 16;
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}
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static void si_ih_set_rptr(struct amdgpu_device *adev)
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{
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WREG32(IH_RB_RPTR, adev->irq.ih.rptr);
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}
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static int si_ih_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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si_ih_set_interrupt_funcs(adev);
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return 0;
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}
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static int si_ih_sw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
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if (r)
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return r;
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return amdgpu_irq_init(adev);
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}
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static int si_ih_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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amdgpu_irq_fini(adev);
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amdgpu_ih_ring_fini(adev);
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return 0;
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}
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static int si_ih_hw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return si_ih_irq_init(adev);
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}
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static int si_ih_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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si_ih_irq_disable(adev);
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return 0;
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}
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static int si_ih_suspend(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return si_ih_hw_fini(adev);
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}
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static int si_ih_resume(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return si_ih_hw_init(adev);
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}
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static bool si_ih_is_idle(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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u32 tmp = RREG32(SRBM_STATUS);
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if (tmp & SRBM_STATUS__IH_BUSY_MASK)
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return false;
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return true;
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}
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static int si_ih_wait_for_idle(void *handle)
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{
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unsigned i;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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for (i = 0; i < adev->usec_timeout; i++) {
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if (si_ih_is_idle(handle))
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return 0;
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udelay(1);
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}
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return -ETIMEDOUT;
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}
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static int si_ih_soft_reset(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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u32 srbm_soft_reset = 0;
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u32 tmp = RREG32(SRBM_STATUS);
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if (tmp & SRBM_STATUS__IH_BUSY_MASK)
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
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if (srbm_soft_reset) {
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tmp = RREG32(SRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(SRBM_SOFT_RESET, tmp);
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tmp = RREG32(SRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~srbm_soft_reset;
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WREG32(SRBM_SOFT_RESET, tmp);
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tmp = RREG32(SRBM_SOFT_RESET);
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udelay(50);
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}
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return 0;
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}
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static int si_ih_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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return 0;
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}
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static int si_ih_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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return 0;
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}
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static const struct amd_ip_funcs si_ih_ip_funcs = {
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.name = "si_ih",
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.early_init = si_ih_early_init,
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.late_init = NULL,
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.sw_init = si_ih_sw_init,
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.sw_fini = si_ih_sw_fini,
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.hw_init = si_ih_hw_init,
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.hw_fini = si_ih_hw_fini,
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.suspend = si_ih_suspend,
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.resume = si_ih_resume,
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.is_idle = si_ih_is_idle,
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.wait_for_idle = si_ih_wait_for_idle,
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.soft_reset = si_ih_soft_reset,
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.set_clockgating_state = si_ih_set_clockgating_state,
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.set_powergating_state = si_ih_set_powergating_state,
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};
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static const struct amdgpu_ih_funcs si_ih_funcs = {
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.get_wptr = si_ih_get_wptr,
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.decode_iv = si_ih_decode_iv,
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.set_rptr = si_ih_set_rptr
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};
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static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
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{
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if (adev->irq.ih_funcs == NULL)
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adev->irq.ih_funcs = &si_ih_funcs;
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}
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const struct amdgpu_ip_block_version si_ih_ip_block =
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{
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.type = AMD_IP_BLOCK_TYPE_IH,
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.major = 1,
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.minor = 0,
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.rev = 0,
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.funcs = &si_ih_ip_funcs,
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};
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