232 lines
6.9 KiB
C
232 lines
6.9 KiB
C
/*
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* Copyright (C) 2016,2017 ARM Limited, All Rights Reserved.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/msi.h>
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#include <linux/sched.h>
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#include <linux/irqchip/arm-gic-v4.h>
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/*
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* WARNING: The blurb below assumes that you understand the
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* intricacies of GICv3, GICv4, and how a guest's view of a GICv3 gets
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* translated into GICv4 commands. So it effectively targets at most
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* two individuals. You know who you are.
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*
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* The core GICv4 code is designed to *avoid* exposing too much of the
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* core GIC code (that would in turn leak into the hypervisor code),
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* and instead provide a hypervisor agnostic interface to the HW (of
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* course, the astute reader will quickly realize that hypervisor
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* agnostic actually means KVM-specific - what were you thinking?).
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*
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* In order to achieve a modicum of isolation, we try to hide most of
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* the GICv4 "stuff" behind normal irqchip operations:
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*
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* - Any guest-visible VLPI is backed by a Linux interrupt (and a
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* physical LPI which gets unmapped when the guest maps the
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* VLPI). This allows the same DevID/EventID pair to be either
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* mapped to the LPI (host) or the VLPI (guest). Note that this is
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* exclusive, and you cannot have both.
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*
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* - Enabling/disabling a VLPI is done by issuing mask/unmask calls.
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*
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* - Guest INT/CLEAR commands are implemented through
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* irq_set_irqchip_state().
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*
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* - The *bizarre* stuff (mapping/unmapping an interrupt to a VLPI, or
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* issuing an INV after changing a priority) gets shoved into the
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* irq_set_vcpu_affinity() method. While this is quite horrible
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* (let's face it, this is the irqchip version of an ioctl), it
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* confines the crap to a single location. And map/unmap really is
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* about setting the affinity of a VLPI to a vcpu, so only INV is
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* majorly out of place. So there.
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*
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* A number of commands are simply not provided by this interface, as
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* they do not make direct sense. For example, MAPD is purely local to
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* the virtual ITS (because it references a virtual device, and the
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* physical ITS is still very much in charge of the physical
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* device). Same goes for things like MAPC (the physical ITS deals
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* with the actual vPE affinity, and not the braindead concept of
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* collection). SYNC is not provided either, as each and every command
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* is followed by a VSYNC. This could be relaxed in the future, should
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* this be seen as a bottleneck (yes, this means *never*).
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*
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* But handling VLPIs is only one side of the job of the GICv4
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* code. The other (darker) side is to take care of the doorbell
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* interrupts which are delivered when a VLPI targeting a non-running
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* vcpu is being made pending.
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*
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* The choice made here is that each vcpu (VPE in old northern GICv4
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* dialect) gets a single doorbell LPI, no matter how many interrupts
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* are targeting it. This has a nice property, which is that the
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* interrupt becomes a handle for the VPE, and that the hypervisor
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* code can manipulate it through the normal interrupt API:
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*
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* - VMs (or rather the VM abstraction that matters to the GIC)
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* contain an irq domain where each interrupt maps to a VPE. In
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* turn, this domain sits on top of the normal LPI allocator, and a
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* specially crafted irq_chip implementation.
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*
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* - mask/unmask do what is expected on the doorbell interrupt.
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*
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* - irq_set_affinity is used to move a VPE from one redistributor to
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* another.
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*
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* - irq_set_vcpu_affinity once again gets hijacked for the purpose of
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* creating a new sub-API, namely scheduling/descheduling a VPE
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* (which involves programming GICR_V{PROP,PEND}BASER) and
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* performing INVALL operations.
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*/
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static struct irq_domain *gic_domain;
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static const struct irq_domain_ops *vpe_domain_ops;
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int its_alloc_vcpu_irqs(struct its_vm *vm)
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{
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int vpe_base_irq, i;
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vm->fwnode = irq_domain_alloc_named_id_fwnode("GICv4-vpe",
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task_pid_nr(current));
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if (!vm->fwnode)
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goto err;
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vm->domain = irq_domain_create_hierarchy(gic_domain, 0, vm->nr_vpes,
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vm->fwnode, vpe_domain_ops,
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vm);
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if (!vm->domain)
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goto err;
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for (i = 0; i < vm->nr_vpes; i++) {
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vm->vpes[i]->its_vm = vm;
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vm->vpes[i]->idai = true;
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}
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vpe_base_irq = __irq_domain_alloc_irqs(vm->domain, -1, vm->nr_vpes,
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NUMA_NO_NODE, vm,
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false, NULL);
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if (vpe_base_irq <= 0)
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goto err;
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for (i = 0; i < vm->nr_vpes; i++)
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vm->vpes[i]->irq = vpe_base_irq + i;
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return 0;
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err:
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if (vm->domain)
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irq_domain_remove(vm->domain);
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if (vm->fwnode)
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irq_domain_free_fwnode(vm->fwnode);
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return -ENOMEM;
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}
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void its_free_vcpu_irqs(struct its_vm *vm)
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{
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irq_domain_free_irqs(vm->vpes[0]->irq, vm->nr_vpes);
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irq_domain_remove(vm->domain);
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irq_domain_free_fwnode(vm->fwnode);
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}
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static int its_send_vpe_cmd(struct its_vpe *vpe, struct its_cmd_info *info)
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{
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return irq_set_vcpu_affinity(vpe->irq, info);
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}
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int its_schedule_vpe(struct its_vpe *vpe, bool on)
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{
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struct its_cmd_info info;
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WARN_ON(preemptible());
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info.cmd_type = on ? SCHEDULE_VPE : DESCHEDULE_VPE;
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return its_send_vpe_cmd(vpe, &info);
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}
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int its_invall_vpe(struct its_vpe *vpe)
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{
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struct its_cmd_info info = {
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.cmd_type = INVALL_VPE,
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};
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return its_send_vpe_cmd(vpe, &info);
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}
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int its_map_vlpi(int irq, struct its_vlpi_map *map)
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{
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struct its_cmd_info info = {
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.cmd_type = MAP_VLPI,
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{
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.map = map,
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},
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};
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/*
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* The host will never see that interrupt firing again, so it
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* is vital that we don't do any lazy masking.
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*/
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irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
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return irq_set_vcpu_affinity(irq, &info);
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}
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int its_get_vlpi(int irq, struct its_vlpi_map *map)
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{
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struct its_cmd_info info = {
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.cmd_type = GET_VLPI,
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{
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.map = map,
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},
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};
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return irq_set_vcpu_affinity(irq, &info);
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}
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int its_unmap_vlpi(int irq)
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{
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irq_clear_status_flags(irq, IRQ_DISABLE_UNLAZY);
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return irq_set_vcpu_affinity(irq, NULL);
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}
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int its_prop_update_vlpi(int irq, u8 config, bool inv)
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{
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struct its_cmd_info info = {
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.cmd_type = inv ? PROP_UPDATE_AND_INV_VLPI : PROP_UPDATE_VLPI,
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{
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.config = config,
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},
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};
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return irq_set_vcpu_affinity(irq, &info);
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}
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int its_init_v4(struct irq_domain *domain, const struct irq_domain_ops *ops)
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{
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if (domain) {
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pr_info("ITS: Enabling GICv4 support\n");
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gic_domain = domain;
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vpe_domain_ops = ops;
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return 0;
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}
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pr_err("ITS: No GICv4 VPE domain allocated\n");
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return -ENODEV;
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}
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