386 lines
9.8 KiB
C
386 lines
9.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Cadence Design Systems Inc.
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*
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* Author: Boris Brezillon <boris.brezillon@bootlin.com>
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*/
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#ifndef I3C_CCC_H
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#define I3C_CCC_H
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#include <linux/bitops.h>
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#include <linux/i3c/device.h>
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/* I3C CCC (Common Command Codes) related definitions */
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#define I3C_CCC_DIRECT BIT(7)
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#define I3C_CCC_ID(id, broadcast) \
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((id) | ((broadcast) ? 0 : I3C_CCC_DIRECT))
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/* Commands valid in both broadcast and unicast modes */
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#define I3C_CCC_ENEC(broadcast) I3C_CCC_ID(0x0, broadcast)
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#define I3C_CCC_DISEC(broadcast) I3C_CCC_ID(0x1, broadcast)
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#define I3C_CCC_ENTAS(as, broadcast) I3C_CCC_ID(0x2 + (as), broadcast)
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#define I3C_CCC_RSTDAA(broadcast) I3C_CCC_ID(0x6, broadcast)
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#define I3C_CCC_SETMWL(broadcast) I3C_CCC_ID(0x9, broadcast)
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#define I3C_CCC_SETMRL(broadcast) I3C_CCC_ID(0xa, broadcast)
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#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28 : 0x98)
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#define I3C_CCC_VENDOR(id, broadcast) ((id) + ((broadcast) ? 0x61 : 0xe0))
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/* Broadcast-only commands */
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#define I3C_CCC_ENTDAA I3C_CCC_ID(0x7, true)
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#define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true)
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#define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true)
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#define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true)
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/* Unicast-only commands */
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#define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false)
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#define I3C_CCC_SETNEWDA I3C_CCC_ID(0x8, false)
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#define I3C_CCC_GETMWL I3C_CCC_ID(0xb, false)
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#define I3C_CCC_GETMRL I3C_CCC_ID(0xc, false)
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#define I3C_CCC_GETPID I3C_CCC_ID(0xd, false)
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#define I3C_CCC_GETBCR I3C_CCC_ID(0xe, false)
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#define I3C_CCC_GETDCR I3C_CCC_ID(0xf, false)
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#define I3C_CCC_GETSTATUS I3C_CCC_ID(0x10, false)
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#define I3C_CCC_GETACCMST I3C_CCC_ID(0x11, false)
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#define I3C_CCC_SETBRGTGT I3C_CCC_ID(0x13, false)
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#define I3C_CCC_GETMXDS I3C_CCC_ID(0x14, false)
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#define I3C_CCC_GETHDRCAP I3C_CCC_ID(0x15, false)
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#define I3C_CCC_GETXTIME I3C_CCC_ID(0x19, false)
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#define I3C_CCC_EVENT_SIR BIT(0)
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#define I3C_CCC_EVENT_MR BIT(1)
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#define I3C_CCC_EVENT_HJ BIT(3)
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/**
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* struct i3c_ccc_events - payload passed to ENEC/DISEC CCC
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*
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* @events: bitmask of I3C_CCC_EVENT_xxx events.
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*
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* Depending on the CCC command, the specific events coming from all devices
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* (broadcast version) or a specific device (unicast version) will be
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* enabled (ENEC) or disabled (DISEC).
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*/
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struct i3c_ccc_events {
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u8 events;
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};
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/**
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* struct i3c_ccc_mwl - payload passed to SETMWL/GETMWL CCC
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*
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* @len: maximum write length in bytes
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*
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* The maximum write length is only applicable to SDR private messages or
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* extended Write CCCs (like SETXTIME).
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*/
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struct i3c_ccc_mwl {
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__be16 len;
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};
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/**
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* struct i3c_ccc_mrl - payload passed to SETMRL/GETMRL CCC
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*
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* @len: maximum read length in bytes
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* @ibi_len: maximum IBI payload length
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*
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* The maximum read length is only applicable to SDR private messages or
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* extended Read CCCs (like GETXTIME).
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* The IBI length is only valid if the I3C slave is IBI capable
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* (%I3C_BCR_IBI_REQ_CAP is set).
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*/
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struct i3c_ccc_mrl {
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__be16 read_len;
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u8 ibi_len;
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} __packed;
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/**
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* struct i3c_ccc_dev_desc - I3C/I2C device descriptor used for DEFSLVS
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*
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* @dyn_addr: dynamic address assigned to the I3C slave or 0 if the entry is
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* describing an I2C slave.
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* @dcr: DCR value (not applicable to entries describing I2C devices)
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* @lvr: LVR value (not applicable to entries describing I3C devices)
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* @bcr: BCR value or 0 if this entry is describing an I2C slave
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* @static_addr: static address or 0 if the device does not have a static
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* address
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*
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* The DEFSLVS command should be passed an array of i3c_ccc_dev_desc
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* descriptors (one entry per I3C/I2C dev controlled by the master).
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*/
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struct i3c_ccc_dev_desc {
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u8 dyn_addr;
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union {
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u8 dcr;
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u8 lvr;
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};
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u8 bcr;
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u8 static_addr;
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};
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/**
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* struct i3c_ccc_defslvs - payload passed to DEFSLVS CCC
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*
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* @count: number of dev descriptors
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* @master: descriptor describing the current master
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* @slaves: array of descriptors describing slaves controlled by the
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* current master
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*
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* Information passed to the broadcast DEFSLVS to propagate device
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* information to all masters currently acting as slaves on the bus.
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* This is only meaningful if you have more than one master.
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*/
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struct i3c_ccc_defslvs {
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u8 count;
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struct i3c_ccc_dev_desc master;
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struct i3c_ccc_dev_desc slaves[0];
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} __packed;
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/**
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* enum i3c_ccc_test_mode - enum listing all available test modes
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*
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* @I3C_CCC_EXIT_TEST_MODE: exit test mode
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* @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
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*/
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enum i3c_ccc_test_mode {
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I3C_CCC_EXIT_TEST_MODE,
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I3C_CCC_VENDOR_TEST_MODE,
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};
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/**
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* struct i3c_ccc_enttm - payload passed to ENTTM CCC
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*
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* @mode: one of the &enum i3c_ccc_test_mode modes
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*
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* Information passed to the ENTTM CCC to instruct an I3C device to enter a
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* specific test mode.
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*/
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struct i3c_ccc_enttm {
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u8 mode;
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};
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/**
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* struct i3c_ccc_setda - payload passed to SETNEWDA and SETDASA CCCs
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*
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* @addr: dynamic address to assign to an I3C device
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*
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* Information passed to the SETNEWDA and SETDASA CCCs to assign/change the
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* dynamic address of an I3C device.
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*/
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struct i3c_ccc_setda {
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u8 addr;
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};
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/**
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* struct i3c_ccc_getpid - payload passed to GETPID CCC
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*
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* @pid: 48 bits PID in big endian
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*/
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struct i3c_ccc_getpid {
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u8 pid[6];
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};
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/**
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* struct i3c_ccc_getbcr - payload passed to GETBCR CCC
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*
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* @bcr: BCR (Bus Characteristic Register) value
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*/
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struct i3c_ccc_getbcr {
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u8 bcr;
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};
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/**
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* struct i3c_ccc_getdcr - payload passed to GETDCR CCC
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*
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* @dcr: DCR (Device Characteristic Register) value
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*/
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struct i3c_ccc_getdcr {
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u8 dcr;
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};
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#define I3C_CCC_STATUS_PENDING_INT(status) ((status) & GENMASK(3, 0))
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#define I3C_CCC_STATUS_PROTOCOL_ERROR BIT(5)
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#define I3C_CCC_STATUS_ACTIVITY_MODE(status) \
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(((status) & GENMASK(7, 6)) >> 6)
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/**
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* struct i3c_ccc_getstatus - payload passed to GETSTATUS CCC
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*
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* @status: status of the I3C slave (see I3C_CCC_STATUS_xxx macros for more
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* information).
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*/
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struct i3c_ccc_getstatus {
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__be16 status;
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};
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/**
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* struct i3c_ccc_getaccmst - payload passed to GETACCMST CCC
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*
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* @newmaster: address of the master taking bus ownership
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*/
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struct i3c_ccc_getaccmst {
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u8 newmaster;
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};
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/**
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* struct i3c_ccc_bridged_slave_desc - bridged slave descriptor
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*
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* @addr: dynamic address of the bridged device
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* @id: ID of the slave device behind the bridge
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*/
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struct i3c_ccc_bridged_slave_desc {
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u8 addr;
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__be16 id;
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} __packed;
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/**
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* struct i3c_ccc_setbrgtgt - payload passed to SETBRGTGT CCC
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*
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* @count: number of bridged slaves
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* @bslaves: bridged slave descriptors
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*/
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struct i3c_ccc_setbrgtgt {
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u8 count;
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struct i3c_ccc_bridged_slave_desc bslaves[0];
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} __packed;
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/**
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* enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
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*/
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enum i3c_sdr_max_data_rate {
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I3C_SDR0_FSCL_MAX,
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I3C_SDR1_FSCL_8MHZ,
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I3C_SDR2_FSCL_6MHZ,
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I3C_SDR3_FSCL_4MHZ,
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I3C_SDR4_FSCL_2MHZ,
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};
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/**
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* enum i3c_tsco - clock to data turn-around
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*/
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enum i3c_tsco {
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I3C_TSCO_8NS,
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I3C_TSCO_9NS,
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I3C_TSCO_10NS,
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I3C_TSCO_11NS,
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I3C_TSCO_12NS,
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};
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#define I3C_CCC_MAX_SDR_FSCL_MASK GENMASK(2, 0)
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#define I3C_CCC_MAX_SDR_FSCL(x) ((x) & I3C_CCC_MAX_SDR_FSCL_MASK)
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/**
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* struct i3c_ccc_getmxds - payload passed to GETMXDS CCC
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*
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* @maxwr: write limitations
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* @maxrd: read limitations
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* @maxrdturn: maximum read turn-around expressed micro-seconds and
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* little-endian formatted
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*/
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struct i3c_ccc_getmxds {
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u8 maxwr;
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u8 maxrd;
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u8 maxrdturn[3];
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} __packed;
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#define I3C_CCC_HDR_MODE(mode) BIT(mode)
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/**
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* struct i3c_ccc_gethdrcap - payload passed to GETHDRCAP CCC
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*
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* @modes: bitmap of supported HDR modes
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*/
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struct i3c_ccc_gethdrcap {
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u8 modes;
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} __packed;
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/**
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* enum i3c_ccc_setxtime_subcmd - SETXTIME sub-commands
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*/
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enum i3c_ccc_setxtime_subcmd {
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I3C_CCC_SETXTIME_ST = 0x7f,
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I3C_CCC_SETXTIME_DT = 0xbf,
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I3C_CCC_SETXTIME_ENTER_ASYNC_MODE0 = 0xdf,
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I3C_CCC_SETXTIME_ENTER_ASYNC_MODE1 = 0xef,
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I3C_CCC_SETXTIME_ENTER_ASYNC_MODE2 = 0xf7,
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I3C_CCC_SETXTIME_ENTER_ASYNC_MODE3 = 0xfb,
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I3C_CCC_SETXTIME_ASYNC_TRIGGER = 0xfd,
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I3C_CCC_SETXTIME_TPH = 0x3f,
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I3C_CCC_SETXTIME_TU = 0x9f,
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I3C_CCC_SETXTIME_ODR = 0x8f,
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};
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/**
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* struct i3c_ccc_setxtime - payload passed to SETXTIME CCC
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*
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* @subcmd: one of the sub-commands ddefined in &enum i3c_ccc_setxtime_subcmd
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* @data: sub-command payload. Amount of data is determined by
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* &i3c_ccc_setxtime->subcmd
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*/
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struct i3c_ccc_setxtime {
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u8 subcmd;
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u8 data[0];
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} __packed;
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#define I3C_CCC_GETXTIME_SYNC_MODE BIT(0)
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#define I3C_CCC_GETXTIME_ASYNC_MODE(x) BIT((x) + 1)
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#define I3C_CCC_GETXTIME_OVERFLOW BIT(7)
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/**
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* struct i3c_ccc_getxtime - payload retrieved from GETXTIME CCC
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*
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* @supported_modes: bitmap describing supported XTIME modes
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* @state: current status (enabled mode and overflow status)
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* @frequency: slave's internal oscillator frequency in 500KHz steps
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* @inaccuracy: slave's internal oscillator inaccuracy in 0.1% steps
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*/
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struct i3c_ccc_getxtime {
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u8 supported_modes;
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u8 state;
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u8 frequency;
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u8 inaccuracy;
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} __packed;
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/**
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* struct i3c_ccc_cmd_payload - CCC payload
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*
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* @len: payload length
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* @data: payload data. This buffer must be DMA-able
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*/
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struct i3c_ccc_cmd_payload {
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u16 len;
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void *data;
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};
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/**
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* struct i3c_ccc_cmd_dest - CCC command destination
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*
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* @addr: can be an I3C device address or the broadcast address if this is a
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* broadcast CCC
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* @payload: payload to be sent to this device or broadcasted
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*/
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struct i3c_ccc_cmd_dest {
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u8 addr;
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struct i3c_ccc_cmd_payload payload;
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};
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/**
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* struct i3c_ccc_cmd - CCC command
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*
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* @rnw: true if the CCC should retrieve data from the device. Only valid for
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* unicast commands
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* @id: CCC command id
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* @ndests: number of destinations. Should always be one for broadcast commands
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* @dests: array of destinations and associated payload for this CCC. Most of
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* the time, only one destination is provided
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* @err: I3C error code
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*/
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struct i3c_ccc_cmd {
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u8 rnw;
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u8 id;
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unsigned int ndests;
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struct i3c_ccc_cmd_dest *dests;
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enum i3c_error_code err;
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};
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#endif /* I3C_CCC_H */
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