522 lines
12 KiB
C
522 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Thunderbolt DMA configuration based mailbox support
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*
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* Copyright (C) 2017, Intel Corporation
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* Authors: Michael Jamet <michael.jamet@intel.com>
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* Mika Westerberg <mika.westerberg@linux.intel.com>
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*/
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include "dma_port.h"
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#include "tb_regs.h"
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#define DMA_PORT_CAP 0x3e
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#define MAIL_DATA 1
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#define MAIL_DATA_DWORDS 16
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#define MAIL_IN 17
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#define MAIL_IN_CMD_SHIFT 28
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#define MAIL_IN_CMD_MASK GENMASK(31, 28)
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#define MAIL_IN_CMD_FLASH_WRITE 0x0
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#define MAIL_IN_CMD_FLASH_UPDATE_AUTH 0x1
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#define MAIL_IN_CMD_FLASH_READ 0x2
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#define MAIL_IN_CMD_POWER_CYCLE 0x4
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#define MAIL_IN_DWORDS_SHIFT 24
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#define MAIL_IN_DWORDS_MASK GENMASK(27, 24)
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#define MAIL_IN_ADDRESS_SHIFT 2
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#define MAIL_IN_ADDRESS_MASK GENMASK(23, 2)
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#define MAIL_IN_CSS BIT(1)
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#define MAIL_IN_OP_REQUEST BIT(0)
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#define MAIL_OUT 18
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#define MAIL_OUT_STATUS_RESPONSE BIT(29)
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#define MAIL_OUT_STATUS_CMD_SHIFT 4
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#define MAIL_OUT_STATUS_CMD_MASK GENMASK(7, 4)
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#define MAIL_OUT_STATUS_MASK GENMASK(3, 0)
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#define MAIL_OUT_STATUS_COMPLETED 0
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#define MAIL_OUT_STATUS_ERR_AUTH 1
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#define MAIL_OUT_STATUS_ERR_ACCESS 2
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#define DMA_PORT_TIMEOUT 5000 /* ms */
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#define DMA_PORT_RETRIES 3
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/**
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* struct tb_dma_port - DMA control port
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* @sw: Switch the DMA port belongs to
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* @port: Switch port number where DMA capability is found
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* @base: Start offset of the mailbox registers
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* @buf: Temporary buffer to store a single block
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*/
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struct tb_dma_port {
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struct tb_switch *sw;
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u8 port;
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u32 base;
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u8 *buf;
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};
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/*
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* When the switch is in safe mode it supports very little functionality
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* so we don't validate that much here.
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*/
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static bool dma_port_match(const struct tb_cfg_request *req,
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const struct ctl_pkg *pkg)
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{
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u64 route = tb_cfg_get_route(pkg->buffer) & ~BIT_ULL(63);
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if (pkg->frame.eof == TB_CFG_PKG_ERROR)
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return true;
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if (pkg->frame.eof != req->response_type)
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return false;
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if (route != tb_cfg_get_route(req->request))
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return false;
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if (pkg->frame.size != req->response_size)
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return false;
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return true;
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}
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static bool dma_port_copy(struct tb_cfg_request *req, const struct ctl_pkg *pkg)
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{
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memcpy(req->response, pkg->buffer, req->response_size);
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return true;
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}
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static int dma_port_read(struct tb_ctl *ctl, void *buffer, u64 route,
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u32 port, u32 offset, u32 length, int timeout_msec)
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{
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struct cfg_read_pkg request = {
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.header = tb_cfg_make_header(route),
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.addr = {
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.seq = 1,
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.port = port,
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.space = TB_CFG_PORT,
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.offset = offset,
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.length = length,
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},
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};
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struct tb_cfg_request *req;
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struct cfg_write_pkg reply;
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struct tb_cfg_result res;
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req = tb_cfg_request_alloc();
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if (!req)
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return -ENOMEM;
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req->match = dma_port_match;
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req->copy = dma_port_copy;
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req->request = &request;
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req->request_size = sizeof(request);
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req->request_type = TB_CFG_PKG_READ;
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req->response = &reply;
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req->response_size = 12 + 4 * length;
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req->response_type = TB_CFG_PKG_READ;
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res = tb_cfg_request_sync(ctl, req, timeout_msec);
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tb_cfg_request_put(req);
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if (res.err)
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return res.err;
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memcpy(buffer, &reply.data, 4 * length);
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return 0;
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}
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static int dma_port_write(struct tb_ctl *ctl, const void *buffer, u64 route,
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u32 port, u32 offset, u32 length, int timeout_msec)
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{
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struct cfg_write_pkg request = {
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.header = tb_cfg_make_header(route),
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.addr = {
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.seq = 1,
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.port = port,
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.space = TB_CFG_PORT,
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.offset = offset,
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.length = length,
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},
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};
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struct tb_cfg_request *req;
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struct cfg_read_pkg reply;
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struct tb_cfg_result res;
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memcpy(&request.data, buffer, length * 4);
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req = tb_cfg_request_alloc();
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if (!req)
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return -ENOMEM;
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req->match = dma_port_match;
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req->copy = dma_port_copy;
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req->request = &request;
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req->request_size = 12 + 4 * length;
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req->request_type = TB_CFG_PKG_WRITE;
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req->response = &reply;
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req->response_size = sizeof(reply);
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req->response_type = TB_CFG_PKG_WRITE;
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res = tb_cfg_request_sync(ctl, req, timeout_msec);
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tb_cfg_request_put(req);
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return res.err;
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}
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static int dma_find_port(struct tb_switch *sw)
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{
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static const int ports[] = { 3, 5, 7 };
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int i;
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/*
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* The DMA (NHI) port is either 3, 5 or 7 depending on the
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* controller. Try all of them.
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*/
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for (i = 0; i < ARRAY_SIZE(ports); i++) {
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u32 type;
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int ret;
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ret = dma_port_read(sw->tb->ctl, &type, tb_route(sw), ports[i],
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2, 1, DMA_PORT_TIMEOUT);
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if (!ret && (type & 0xffffff) == TB_TYPE_NHI)
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return ports[i];
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}
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return -ENODEV;
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}
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/**
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* dma_port_alloc() - Finds DMA control port from a switch pointed by route
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* @sw: Switch from where find the DMA port
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*
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* Function checks if the switch NHI port supports DMA configuration
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* based mailbox capability and if it does, allocates and initializes
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* DMA port structure. Returns %NULL if the capabity was not found.
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*
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* The DMA control port is functional also when the switch is in safe
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* mode.
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*/
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struct tb_dma_port *dma_port_alloc(struct tb_switch *sw)
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{
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struct tb_dma_port *dma;
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int port;
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port = dma_find_port(sw);
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if (port < 0)
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return NULL;
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dma = kzalloc(sizeof(*dma), GFP_KERNEL);
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if (!dma)
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return NULL;
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dma->buf = kmalloc_array(MAIL_DATA_DWORDS, sizeof(u32), GFP_KERNEL);
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if (!dma->buf) {
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kfree(dma);
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return NULL;
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}
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dma->sw = sw;
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dma->port = port;
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dma->base = DMA_PORT_CAP;
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return dma;
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}
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/**
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* dma_port_free() - Release DMA control port structure
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* @dma: DMA control port
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*/
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void dma_port_free(struct tb_dma_port *dma)
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{
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if (dma) {
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kfree(dma->buf);
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kfree(dma);
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}
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}
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static int dma_port_wait_for_completion(struct tb_dma_port *dma,
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unsigned int timeout)
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{
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unsigned long end = jiffies + msecs_to_jiffies(timeout);
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struct tb_switch *sw = dma->sw;
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do {
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int ret;
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u32 in;
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ret = dma_port_read(sw->tb->ctl, &in, tb_route(sw), dma->port,
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dma->base + MAIL_IN, 1, 50);
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if (ret) {
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if (ret != -ETIMEDOUT)
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return ret;
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} else if (!(in & MAIL_IN_OP_REQUEST)) {
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return 0;
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}
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usleep_range(50, 100);
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} while (time_before(jiffies, end));
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return -ETIMEDOUT;
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}
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static int status_to_errno(u32 status)
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{
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switch (status & MAIL_OUT_STATUS_MASK) {
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case MAIL_OUT_STATUS_COMPLETED:
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return 0;
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case MAIL_OUT_STATUS_ERR_AUTH:
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return -EINVAL;
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case MAIL_OUT_STATUS_ERR_ACCESS:
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return -EACCES;
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}
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return -EIO;
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}
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static int dma_port_request(struct tb_dma_port *dma, u32 in,
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unsigned int timeout)
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{
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struct tb_switch *sw = dma->sw;
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u32 out;
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int ret;
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ret = dma_port_write(sw->tb->ctl, &in, tb_route(sw), dma->port,
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dma->base + MAIL_IN, 1, DMA_PORT_TIMEOUT);
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if (ret)
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return ret;
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ret = dma_port_wait_for_completion(dma, timeout);
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if (ret)
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return ret;
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ret = dma_port_read(sw->tb->ctl, &out, tb_route(sw), dma->port,
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dma->base + MAIL_OUT, 1, DMA_PORT_TIMEOUT);
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if (ret)
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return ret;
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return status_to_errno(out);
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}
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static int dma_port_flash_read_block(struct tb_dma_port *dma, u32 address,
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void *buf, u32 size)
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{
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struct tb_switch *sw = dma->sw;
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u32 in, dwaddress, dwords;
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int ret;
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dwaddress = address / 4;
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dwords = size / 4;
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in = MAIL_IN_CMD_FLASH_READ << MAIL_IN_CMD_SHIFT;
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if (dwords < MAIL_DATA_DWORDS)
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in |= (dwords << MAIL_IN_DWORDS_SHIFT) & MAIL_IN_DWORDS_MASK;
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in |= (dwaddress << MAIL_IN_ADDRESS_SHIFT) & MAIL_IN_ADDRESS_MASK;
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in |= MAIL_IN_OP_REQUEST;
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ret = dma_port_request(dma, in, DMA_PORT_TIMEOUT);
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if (ret)
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return ret;
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return dma_port_read(sw->tb->ctl, buf, tb_route(sw), dma->port,
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dma->base + MAIL_DATA, dwords, DMA_PORT_TIMEOUT);
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}
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static int dma_port_flash_write_block(struct tb_dma_port *dma, u32 address,
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const void *buf, u32 size)
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{
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struct tb_switch *sw = dma->sw;
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u32 in, dwaddress, dwords;
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int ret;
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dwords = size / 4;
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/* Write the block to MAIL_DATA registers */
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ret = dma_port_write(sw->tb->ctl, buf, tb_route(sw), dma->port,
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dma->base + MAIL_DATA, dwords, DMA_PORT_TIMEOUT);
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if (ret)
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return ret;
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in = MAIL_IN_CMD_FLASH_WRITE << MAIL_IN_CMD_SHIFT;
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/* CSS header write is always done to the same magic address */
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if (address >= DMA_PORT_CSS_ADDRESS) {
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dwaddress = DMA_PORT_CSS_ADDRESS;
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in |= MAIL_IN_CSS;
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} else {
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dwaddress = address / 4;
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}
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in |= ((dwords - 1) << MAIL_IN_DWORDS_SHIFT) & MAIL_IN_DWORDS_MASK;
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in |= (dwaddress << MAIL_IN_ADDRESS_SHIFT) & MAIL_IN_ADDRESS_MASK;
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in |= MAIL_IN_OP_REQUEST;
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return dma_port_request(dma, in, DMA_PORT_TIMEOUT);
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}
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/**
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* dma_port_flash_read() - Read from active flash region
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* @dma: DMA control port
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* @address: Address relative to the start of active region
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* @buf: Buffer where the data is read
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* @size: Size of the buffer
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*/
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int dma_port_flash_read(struct tb_dma_port *dma, unsigned int address,
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void *buf, size_t size)
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{
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unsigned int retries = DMA_PORT_RETRIES;
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unsigned int offset;
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offset = address & 3;
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address = address & ~3;
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do {
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u32 nbytes = min_t(u32, size, MAIL_DATA_DWORDS * 4);
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int ret;
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ret = dma_port_flash_read_block(dma, address, dma->buf,
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ALIGN(nbytes, 4));
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if (ret) {
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if (ret == -ETIMEDOUT) {
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if (retries--)
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continue;
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ret = -EIO;
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}
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return ret;
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}
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memcpy(buf, dma->buf + offset, nbytes);
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size -= nbytes;
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address += nbytes;
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buf += nbytes;
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} while (size > 0);
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return 0;
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}
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/**
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* dma_port_flash_write() - Write to non-active flash region
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* @dma: DMA control port
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* @address: Address relative to the start of non-active region
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* @buf: Data to write
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* @size: Size of the buffer
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*
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* Writes block of data to the non-active flash region of the switch. If
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* the address is given as %DMA_PORT_CSS_ADDRESS the block is written
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* using CSS command.
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*/
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int dma_port_flash_write(struct tb_dma_port *dma, unsigned int address,
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const void *buf, size_t size)
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{
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unsigned int retries = DMA_PORT_RETRIES;
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unsigned int offset;
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if (address >= DMA_PORT_CSS_ADDRESS) {
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offset = 0;
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if (size > DMA_PORT_CSS_MAX_SIZE)
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return -E2BIG;
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} else {
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offset = address & 3;
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address = address & ~3;
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}
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do {
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u32 nbytes = min_t(u32, size, MAIL_DATA_DWORDS * 4);
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int ret;
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memcpy(dma->buf + offset, buf, nbytes);
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ret = dma_port_flash_write_block(dma, address, buf, nbytes);
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if (ret) {
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if (ret == -ETIMEDOUT) {
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if (retries--)
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continue;
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ret = -EIO;
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}
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return ret;
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}
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size -= nbytes;
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address += nbytes;
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buf += nbytes;
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} while (size > 0);
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return 0;
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}
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/**
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* dma_port_flash_update_auth() - Starts flash authenticate cycle
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* @dma: DMA control port
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*
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* Starts the flash update authentication cycle. If the image in the
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* non-active area was valid, the switch starts upgrade process where
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* active and non-active area get swapped in the end. Caller should call
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* dma_port_flash_update_auth_status() to get status of this command.
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* This is because if the switch in question is root switch the
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* thunderbolt host controller gets reset as well.
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*/
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int dma_port_flash_update_auth(struct tb_dma_port *dma)
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{
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u32 in;
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in = MAIL_IN_CMD_FLASH_UPDATE_AUTH << MAIL_IN_CMD_SHIFT;
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in |= MAIL_IN_OP_REQUEST;
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return dma_port_request(dma, in, 150);
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}
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/**
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* dma_port_flash_update_auth_status() - Reads status of update auth command
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* @dma: DMA control port
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* @status: Status code of the operation
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*
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* The function checks if there is status available from the last update
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* auth command. Returns %0 if there is no status and no further
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* action is required. If there is status, %1 is returned instead and
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* @status holds the failure code.
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*
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* Negative return means there was an error reading status from the
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* switch.
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*/
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int dma_port_flash_update_auth_status(struct tb_dma_port *dma, u32 *status)
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{
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struct tb_switch *sw = dma->sw;
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u32 out, cmd;
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int ret;
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ret = dma_port_read(sw->tb->ctl, &out, tb_route(sw), dma->port,
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dma->base + MAIL_OUT, 1, DMA_PORT_TIMEOUT);
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if (ret)
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return ret;
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/* Check if the status relates to flash update auth */
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cmd = (out & MAIL_OUT_STATUS_CMD_MASK) >> MAIL_OUT_STATUS_CMD_SHIFT;
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if (cmd == MAIL_IN_CMD_FLASH_UPDATE_AUTH) {
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if (status)
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*status = out & MAIL_OUT_STATUS_MASK;
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/* Reset is needed in any case */
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return 1;
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}
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return 0;
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}
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/**
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* dma_port_power_cycle() - Power cycles the switch
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* @dma: DMA control port
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*
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* Triggers power cycle to the switch.
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*/
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int dma_port_power_cycle(struct tb_dma_port *dma)
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{
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u32 in;
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in = MAIL_IN_CMD_POWER_CYCLE << MAIL_IN_CMD_SHIFT;
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in |= MAIL_IN_OP_REQUEST;
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return dma_port_request(dma, in, 150);
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}
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