201 lines
5.0 KiB
C
201 lines
5.0 KiB
C
/*
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* Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_MXC_H__
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#define __ASM_ARCH_MXC_H__
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#include <linux/types.h>
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#ifndef __ASM_ARCH_MXC_HARDWARE_H__
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#error "Do not include directly."
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#endif
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#define MXC_CPU_MX1 1
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#define MXC_CPU_MX21 21
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#define MXC_CPU_MX25 25
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#define MXC_CPU_MX27 27
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#define MXC_CPU_MX31 31
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#define MXC_CPU_MX35 35
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#define MXC_CPU_MX50 50
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#define MXC_CPU_MX51 51
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#define MXC_CPU_MX53 53
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#define IMX_CHIP_REVISION_1_0 0x10
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#define IMX_CHIP_REVISION_1_1 0x11
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#define IMX_CHIP_REVISION_1_2 0x12
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#define IMX_CHIP_REVISION_1_3 0x13
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#define IMX_CHIP_REVISION_2_0 0x20
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#define IMX_CHIP_REVISION_2_1 0x21
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#define IMX_CHIP_REVISION_2_2 0x22
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#define IMX_CHIP_REVISION_2_3 0x23
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#define IMX_CHIP_REVISION_3_0 0x30
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#define IMX_CHIP_REVISION_3_1 0x31
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#define IMX_CHIP_REVISION_3_2 0x32
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#define IMX_CHIP_REVISION_3_3 0x33
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#define IMX_CHIP_REVISION_UNKNOWN 0xff
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#define IMX_CHIP_REVISION_1_0_STRING "1.0"
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#define IMX_CHIP_REVISION_1_1_STRING "1.1"
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#define IMX_CHIP_REVISION_1_2_STRING "1.2"
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#define IMX_CHIP_REVISION_1_3_STRING "1.3"
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#define IMX_CHIP_REVISION_2_0_STRING "2.0"
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#define IMX_CHIP_REVISION_2_1_STRING "2.1"
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#define IMX_CHIP_REVISION_2_2_STRING "2.2"
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#define IMX_CHIP_REVISION_2_3_STRING "2.3"
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#define IMX_CHIP_REVISION_3_0_STRING "3.0"
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#define IMX_CHIP_REVISION_3_1_STRING "3.1"
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#define IMX_CHIP_REVISION_3_2_STRING "3.2"
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#define IMX_CHIP_REVISION_3_3_STRING "3.3"
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#define IMX_CHIP_REVISION_UNKNOWN_STRING "unknown"
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#ifndef __ASSEMBLY__
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extern unsigned int __mxc_cpu_type;
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#endif
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#ifdef CONFIG_SOC_IMX1
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX1
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# endif
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# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
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#else
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# define cpu_is_mx1() (0)
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#endif
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#ifdef CONFIG_SOC_IMX21
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX21
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# endif
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# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
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#else
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# define cpu_is_mx21() (0)
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#endif
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#ifdef CONFIG_SOC_IMX25
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX25
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# endif
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# define cpu_is_mx25() (mxc_cpu_type == MXC_CPU_MX25)
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#else
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# define cpu_is_mx25() (0)
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#endif
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#ifdef CONFIG_SOC_IMX27
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX27
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# endif
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# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
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#else
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# define cpu_is_mx27() (0)
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#endif
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#ifdef CONFIG_SOC_IMX31
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX31
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# endif
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# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
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#else
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# define cpu_is_mx31() (0)
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#endif
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#ifdef CONFIG_SOC_IMX35
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX35
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# endif
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# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
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#else
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# define cpu_is_mx35() (0)
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#endif
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#ifdef CONFIG_SOC_IMX50
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX50
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# endif
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# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
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#else
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# define cpu_is_mx50() (0)
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#endif
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#ifdef CONFIG_SOC_IMX51
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX51
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# endif
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# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51)
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#else
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# define cpu_is_mx51() (0)
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#endif
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#ifdef CONFIG_SOC_IMX53
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# ifdef mxc_cpu_type
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# undef mxc_cpu_type
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# define mxc_cpu_type __mxc_cpu_type
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# else
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# define mxc_cpu_type MXC_CPU_MX53
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# endif
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# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
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#else
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# define cpu_is_mx53() (0)
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#endif
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#ifndef __ASSEMBLY__
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struct cpu_op {
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u32 cpu_rate;
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};
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int tzic_enable_wake(int is_idle);
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enum mxc_cpu_pwr_mode {
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WAIT_CLOCKED, /* wfi only */
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WAIT_UNCLOCKED, /* WAIT */
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WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
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STOP_POWER_ON, /* just STOP */
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STOP_POWER_OFF, /* STOP + SRPG */
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};
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extern struct cpu_op *(*get_cpu_op)(int *op);
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#endif
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#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
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#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
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#endif /* __ASM_ARCH_MXC_H__ */
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