293 lines
9.3 KiB
C
293 lines
9.3 KiB
C
/* linux/arch/arm/mach-msm/board-trout-mddi.c
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** Author: Brian Swetland <swetland@google.com>
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*/
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#include <linux/gpio.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/leds.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/system_info.h>
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#include <linux/platform_data/video-msm_fb.h>
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#include <mach/vreg.h>
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#include "board-trout.h"
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#include "proc_comm.h"
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#include "clock-pcom.h"
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#include "devices.h"
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#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
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#define MDDI_CLIENT_CORE_BASE 0x108000
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#define LCD_CONTROL_BLOCK_BASE 0x110000
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#define SPI_BLOCK_BASE 0x120000
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#define I2C_BLOCK_BASE 0x130000
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#define PWM_BLOCK_BASE 0x140000
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#define GPIO_BLOCK_BASE 0x150000
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#define SYSTEM_BLOCK1_BASE 0x160000
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#define SYSTEM_BLOCK2_BASE 0x170000
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#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
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#define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C)
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#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
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#define V_VDDE2E_VDD2_GPIO 0
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#define MDDI_RST_N 82
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#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
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#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
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#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
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#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
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#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
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#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
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#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
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#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
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#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
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#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
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#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
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#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
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#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
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#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
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#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
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#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
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#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
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#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
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#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
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#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
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#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
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#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
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#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
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#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
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#define START (LCD_CONTROL_BLOCK_BASE|0x08)
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#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
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#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
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#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
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#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
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#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
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#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
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#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
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#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
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#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
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#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
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#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
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#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
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#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
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#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
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#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
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#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
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#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
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#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
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#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
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#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
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#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
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#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
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#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
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#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
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#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
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#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
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#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
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#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
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#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
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#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
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#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
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#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
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#define SSICTL (SPI_BLOCK_BASE|0x00)
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#define SSITIME (SPI_BLOCK_BASE|0x04)
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#define SSITX (SPI_BLOCK_BASE|0x08)
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#define SSIRX (SPI_BLOCK_BASE|0x0C)
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#define SSIINTC (SPI_BLOCK_BASE|0x10)
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#define SSIINTS (SPI_BLOCK_BASE|0x14)
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#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
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#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
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#define SSIID (SPI_BLOCK_BASE|0x20)
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#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
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#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
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#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
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#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
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#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
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#define GPIODATA (GPIO_BLOCK_BASE|0x00)
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#define GPIODIR (GPIO_BLOCK_BASE|0x04)
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#define GPIOIS (GPIO_BLOCK_BASE|0x08)
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#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
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#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
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#define GPIOIE (GPIO_BLOCK_BASE|0x14)
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#define GPIORIS (GPIO_BLOCK_BASE|0x18)
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#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
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#define GPIOIC (GPIO_BLOCK_BASE|0x20)
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#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
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#define GPIOPC (GPIO_BLOCK_BASE|0x28)
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#define GPIOID (GPIO_BLOCK_BASE|0x30)
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#define SPI_WRITE(reg, val) \
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{ SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
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{ 0, 5 },
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#define SPI_WRITE1(reg) \
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{ SSITX, (reg) & 0xff }, \
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{ 0, 5 },
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struct mddi_table {
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uint32_t reg;
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uint32_t value;
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};
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static struct mddi_table mddi_toshiba_init_table[] = {
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{ DPSET0, 0x09e90046 },
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{ DPSET1, 0x00000118 },
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{ DPSUS, 0x00000000 },
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{ DPRUN, 0x00000001 },
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{ 1, 14 }, /* msleep 14 */
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{ SYSCKENA, 0x00000001 },
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{ CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */
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{ GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */
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{ GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */
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{ GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */
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{ GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */
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{ WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */
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{ GPIOIBE, 0x000003FF },
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{ GPIOIS, 0x00000000 },
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{ GPIOIC, 0x000003FF },
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{ GPIOIE, 0x00000000 },
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{ GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
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{ 1, 1 }, /* msleep 1 */
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{ GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */
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{ DRAMPWR, 0x00000001 }, /* eDRAM power */
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};
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#define GPIOSEL_VWAKEINT (1U << 0)
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#define INTMASK_VWAKEOUT (1U << 0)
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static int trout_new_backlight = 1;
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static struct vreg *vreg_mddi_1v5;
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static struct vreg *vreg_lcm_2v85;
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static void trout_process_mddi_table(struct msm_mddi_client_data *client_data,
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struct mddi_table *table, size_t count)
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{
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int i;
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for (i = 0; i < count; i++) {
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uint32_t reg = table[i].reg;
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uint32_t value = table[i].value;
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if (reg == 0)
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udelay(value);
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else if (reg == 1)
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msleep(value);
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else
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client_data->remote_write(client_data, value, reg);
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}
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}
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static int trout_mddi_toshiba_client_init(
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struct msm_mddi_bridge_platform_data *bridge_data,
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struct msm_mddi_client_data *client_data)
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{
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int panel_id;
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client_data->auto_hibernate(client_data, 0);
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trout_process_mddi_table(client_data, mddi_toshiba_init_table,
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ARRAY_SIZE(mddi_toshiba_init_table));
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client_data->auto_hibernate(client_data, 1);
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panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3;
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if (panel_id > 1) {
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printk(KERN_WARNING "unknown panel id at mddi_enable\n");
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return -1;
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}
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return 0;
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}
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static int trout_mddi_toshiba_client_uninit(
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struct msm_mddi_bridge_platform_data *bridge_data,
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struct msm_mddi_client_data *client_data)
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{
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return 0;
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}
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static struct resource resources_msm_fb[] = {
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{
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.start = MSM_FB_BASE,
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.end = MSM_FB_BASE + MSM_FB_SIZE,
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.flags = IORESOURCE_MEM,
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},
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};
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struct msm_mddi_bridge_platform_data toshiba_client_data = {
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.init = trout_mddi_toshiba_client_init,
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.uninit = trout_mddi_toshiba_client_uninit,
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.fb_data = {
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.xres = 320,
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.yres = 480,
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.width = 45,
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.height = 67,
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.output_format = 0,
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},
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};
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static struct msm_mddi_platform_data mddi_pdata = {
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.clk_rate = 122880000,
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.fb_resource = resources_msm_fb,
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.num_clients = 1,
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.client_platform_data = {
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{
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.product_id = (0xd263 << 16 | 0),
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.name = "mddi_c_d263_0000",
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.id = 0,
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.client_data = &toshiba_client_data,
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.clk_rate = 0,
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},
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},
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};
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int __init trout_init_panel(void)
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{
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int rc;
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if (!machine_is_trout())
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return 0;
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vreg_mddi_1v5 = vreg_get(0, "gp2");
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if (IS_ERR(vreg_mddi_1v5))
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return PTR_ERR(vreg_mddi_1v5);
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vreg_lcm_2v85 = vreg_get(0, "gp4");
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if (IS_ERR(vreg_lcm_2v85))
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return PTR_ERR(vreg_lcm_2v85);
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trout_new_backlight = system_rev >= 5;
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if (trout_new_backlight) {
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uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT,
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GPIO_NO_PULL, GPIO_8MA);
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msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
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} else {
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uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
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GPIO_NO_PULL, GPIO_8MA);
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uint32_t id = P_GP_CLK;
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uint32_t rate = 19200000;
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msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
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msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
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if (id < 0)
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pr_err("trout_init_panel: set clock rate failed\n");
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}
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rc = platform_device_register(&msm_device_mdp);
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if (rc)
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return rc;
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msm_device_mddi0.dev.platform_data = &mddi_pdata;
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return platform_device_register(&msm_device_mddi0);
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}
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device_initcall(trout_init_panel);
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