328 lines
10 KiB
C
328 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* GPIO driver for the WinSystems WS16C48
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* Copyright (C) 2016 William Breathitt Gray
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*/
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/gpio/regmap.h>
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#include <linux/irq.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#define WS16C48_EXTENT 11
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#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
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static unsigned int base[MAX_NUM_WS16C48];
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static unsigned int num_ws16c48;
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module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
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MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
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static unsigned int irq[MAX_NUM_WS16C48];
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static unsigned int num_irq;
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module_param_hw_array(irq, uint, irq, &num_irq, 0);
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MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
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#define WS16C48_DAT_BASE 0x0
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#define WS16C48_PAGE_LOCK 0x7
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#define WS16C48_PAGE_BASE 0x8
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#define WS16C48_POL WS16C48_PAGE_BASE
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#define WS16C48_ENAB WS16C48_PAGE_BASE
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#define WS16C48_INT_ID WS16C48_PAGE_BASE
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#define PAGE_LOCK_PAGE_FIELD GENMASK(7, 6)
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#define POL_PAGE u8_encode_bits(1, PAGE_LOCK_PAGE_FIELD)
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#define ENAB_PAGE u8_encode_bits(2, PAGE_LOCK_PAGE_FIELD)
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#define INT_ID_PAGE u8_encode_bits(3, PAGE_LOCK_PAGE_FIELD)
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static const struct regmap_range ws16c48_wr_ranges[] = {
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regmap_reg_range(0x0, 0x5), regmap_reg_range(0x7, 0xA),
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};
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static const struct regmap_range ws16c48_rd_ranges[] = {
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regmap_reg_range(0x0, 0xA),
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};
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static const struct regmap_range ws16c48_volatile_ranges[] = {
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regmap_reg_range(0x0, 0x6), regmap_reg_range(0x8, 0xA),
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};
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static const struct regmap_access_table ws16c48_wr_table = {
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.yes_ranges = ws16c48_wr_ranges,
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.n_yes_ranges = ARRAY_SIZE(ws16c48_wr_ranges),
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};
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static const struct regmap_access_table ws16c48_rd_table = {
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.yes_ranges = ws16c48_rd_ranges,
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.n_yes_ranges = ARRAY_SIZE(ws16c48_rd_ranges),
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};
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static const struct regmap_access_table ws16c48_volatile_table = {
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.yes_ranges = ws16c48_volatile_ranges,
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.n_yes_ranges = ARRAY_SIZE(ws16c48_volatile_ranges),
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};
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static const struct regmap_config ws16c48_regmap_config = {
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.reg_bits = 8,
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.reg_stride = 1,
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.val_bits = 8,
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.io_port = true,
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.wr_table = &ws16c48_wr_table,
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.rd_table = &ws16c48_rd_table,
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.volatile_table = &ws16c48_volatile_table,
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.cache_type = REGCACHE_FLAT,
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.use_raw_spinlock = true,
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};
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#define WS16C48_NGPIO_PER_REG 8
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#define WS16C48_REGMAP_IRQ(_id) \
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[_id] = { \
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.reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
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.mask = BIT((_id) % WS16C48_NGPIO_PER_REG), \
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.type = { \
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.type_reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
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.types_supported = IRQ_TYPE_EDGE_BOTH, \
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}, \
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}
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/* Only the first 24 lines (Port 0-2) support interrupts */
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#define WS16C48_NUM_IRQS 24
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static const struct regmap_irq ws16c48_regmap_irqs[WS16C48_NUM_IRQS] = {
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WS16C48_REGMAP_IRQ(0), WS16C48_REGMAP_IRQ(1), WS16C48_REGMAP_IRQ(2), /* 0-2 */
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WS16C48_REGMAP_IRQ(3), WS16C48_REGMAP_IRQ(4), WS16C48_REGMAP_IRQ(5), /* 3-5 */
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WS16C48_REGMAP_IRQ(6), WS16C48_REGMAP_IRQ(7), WS16C48_REGMAP_IRQ(8), /* 6-8 */
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WS16C48_REGMAP_IRQ(9), WS16C48_REGMAP_IRQ(10), WS16C48_REGMAP_IRQ(11), /* 9-11 */
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WS16C48_REGMAP_IRQ(12), WS16C48_REGMAP_IRQ(13), WS16C48_REGMAP_IRQ(14), /* 12-14 */
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WS16C48_REGMAP_IRQ(15), WS16C48_REGMAP_IRQ(16), WS16C48_REGMAP_IRQ(17), /* 15-17 */
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WS16C48_REGMAP_IRQ(18), WS16C48_REGMAP_IRQ(19), WS16C48_REGMAP_IRQ(20), /* 18-20 */
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WS16C48_REGMAP_IRQ(21), WS16C48_REGMAP_IRQ(22), WS16C48_REGMAP_IRQ(23), /* 21-23 */
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};
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/**
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* struct ws16c48_gpio - GPIO device private data structure
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* @map: regmap for the device
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* @lock: synchronization lock to prevent I/O race conditions
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* @irq_mask: I/O bits affected by interrupts
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*/
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struct ws16c48_gpio {
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struct regmap *map;
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raw_spinlock_t lock;
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u8 irq_mask[WS16C48_NUM_IRQS / WS16C48_NGPIO_PER_REG];
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};
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static int ws16c48_handle_pre_irq(void *const irq_drv_data) __acquires(&ws16c48gpio->lock)
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{
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struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
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/* Lock to prevent Page/Lock register change while we handle IRQ */
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raw_spin_lock(&ws16c48gpio->lock);
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return 0;
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}
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static int ws16c48_handle_post_irq(void *const irq_drv_data) __releases(&ws16c48gpio->lock)
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{
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struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
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raw_spin_unlock(&ws16c48gpio->lock);
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return 0;
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}
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static int ws16c48_handle_mask_sync(const int index, const unsigned int mask_buf_def,
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const unsigned int mask_buf, void *const irq_drv_data)
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{
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struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
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unsigned long flags;
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int ret = 0;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* exit early if no change since the last mask sync */
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if (mask_buf == ws16c48gpio->irq_mask[index])
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goto exit_unlock;
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ws16c48gpio->irq_mask[index] = mask_buf;
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ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, ENAB_PAGE);
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if (ret)
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goto exit_unlock;
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/* Update ENAB register (inverted mask) */
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ret = regmap_write(ws16c48gpio->map, WS16C48_ENAB + index, ~mask_buf);
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if (ret)
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goto exit_unlock;
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ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
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if (ret)
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goto exit_unlock;
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exit_unlock:
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return ret;
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}
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static int ws16c48_set_type_config(unsigned int **const buf, const unsigned int type,
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const struct regmap_irq *const irq_data, const int idx,
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void *const irq_drv_data)
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{
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struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
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unsigned int polarity;
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unsigned long flags;
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int ret;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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polarity = irq_data->mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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polarity = 0;
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break;
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default:
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return -EINVAL;
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}
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, POL_PAGE);
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if (ret)
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goto exit_unlock;
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/* Set interrupt polarity */
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ret = regmap_update_bits(ws16c48gpio->map, WS16C48_POL + idx, irq_data->mask, polarity);
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if (ret)
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goto exit_unlock;
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ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
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if (ret)
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goto exit_unlock;
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exit_unlock:
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return ret;
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}
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#define WS16C48_NGPIO 48
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static const char *ws16c48_names[WS16C48_NGPIO] = {
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"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
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"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
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"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
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"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
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"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
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"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
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"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
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"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
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"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
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"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
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"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
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"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
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};
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static int ws16c48_irq_init_hw(struct regmap *const map)
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{
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int err;
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err = regmap_write(map, WS16C48_PAGE_LOCK, ENAB_PAGE);
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if (err)
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return err;
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/* Disable interrupts for all lines */
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err = regmap_write(map, WS16C48_ENAB + 0, 0x00);
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if (err)
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return err;
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err = regmap_write(map, WS16C48_ENAB + 1, 0x00);
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if (err)
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return err;
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err = regmap_write(map, WS16C48_ENAB + 2, 0x00);
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if (err)
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return err;
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return regmap_write(map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
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}
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static int ws16c48_probe(struct device *dev, unsigned int id)
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{
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struct ws16c48_gpio *ws16c48gpio;
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const char *const name = dev_name(dev);
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int err;
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struct gpio_regmap_config gpio_config = {};
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void __iomem *regs;
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struct regmap_irq_chip *chip;
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struct regmap_irq_chip_data *chip_data;
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ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
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if (!ws16c48gpio)
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return -ENOMEM;
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if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
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dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
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base[id], base[id] + WS16C48_EXTENT);
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return -EBUSY;
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}
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regs = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
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if (!regs)
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return -ENOMEM;
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ws16c48gpio->map = devm_regmap_init_mmio(dev, regs, &ws16c48_regmap_config);
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if (IS_ERR(ws16c48gpio->map))
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return dev_err_probe(dev, PTR_ERR(ws16c48gpio->map),
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"Unable to initialize register map\n");
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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chip->name = name;
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chip->status_base = WS16C48_INT_ID;
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chip->mask_base = WS16C48_ENAB;
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chip->ack_base = WS16C48_INT_ID;
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chip->num_regs = 3;
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chip->irqs = ws16c48_regmap_irqs;
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chip->num_irqs = ARRAY_SIZE(ws16c48_regmap_irqs);
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chip->handle_pre_irq = ws16c48_handle_pre_irq;
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chip->handle_post_irq = ws16c48_handle_post_irq;
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chip->handle_mask_sync = ws16c48_handle_mask_sync;
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chip->set_type_config = ws16c48_set_type_config;
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chip->irq_drv_data = ws16c48gpio;
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raw_spin_lock_init(&ws16c48gpio->lock);
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/* Initialize to prevent spurious interrupts before we're ready */
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err = ws16c48_irq_init_hw(ws16c48gpio->map);
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if (err)
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return err;
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err = devm_regmap_add_irq_chip(dev, ws16c48gpio->map, irq[id], 0, 0, chip, &chip_data);
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if (err)
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return dev_err_probe(dev, err, "IRQ registration failed\n");
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gpio_config.parent = dev;
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gpio_config.regmap = ws16c48gpio->map;
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gpio_config.ngpio = WS16C48_NGPIO;
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gpio_config.names = ws16c48_names;
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gpio_config.reg_dat_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
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gpio_config.reg_set_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
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/* Setting a GPIO to 0 allows it to be used as an input */
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gpio_config.reg_dir_out_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
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gpio_config.ngpio_per_reg = WS16C48_NGPIO_PER_REG;
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gpio_config.irq_domain = regmap_irq_get_domain(chip_data);
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return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config));
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}
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static struct isa_driver ws16c48_driver = {
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.probe = ws16c48_probe,
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.driver = {
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.name = "ws16c48"
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},
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};
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module_isa_driver_with_irq(ws16c48_driver, num_ws16c48, num_irq);
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MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
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MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
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MODULE_LICENSE("GPL v2");
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