280 lines
6.9 KiB
C
280 lines
6.9 KiB
C
#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/dmar.h>
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#include <linux/cpu.h>
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#include <asm/smp.h>
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#include <asm/x2apic.h>
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static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
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static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster);
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static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
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static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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return x2apic_enabled();
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}
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static inline u32 x2apic_cluster(int cpu)
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{
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return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16;
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}
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static void x2apic_send_IPI(int cpu, int vector)
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{
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u32 dest = per_cpu(x86_cpu_to_logical_apicid, cpu);
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x2apic_wrmsr_fence();
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__x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL);
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}
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static void
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__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
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{
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struct cpumask *cpus_in_cluster_ptr;
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struct cpumask *ipi_mask_ptr;
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unsigned int cpu, this_cpu;
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unsigned long flags;
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u32 dest;
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x2apic_wrmsr_fence();
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local_irq_save(flags);
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this_cpu = smp_processor_id();
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/*
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* We are to modify mask, so we need an own copy
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* and be sure it's manipulated with irq off.
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*/
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ipi_mask_ptr = this_cpu_cpumask_var_ptr(ipi_mask);
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cpumask_copy(ipi_mask_ptr, mask);
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/*
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* The idea is to send one IPI per cluster.
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*/
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for_each_cpu(cpu, ipi_mask_ptr) {
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unsigned long i;
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cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu);
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dest = 0;
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/* Collect cpus in cluster. */
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for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) {
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if (apic_dest == APIC_DEST_ALLINC || i != this_cpu)
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dest |= per_cpu(x86_cpu_to_logical_apicid, i);
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}
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if (!dest)
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continue;
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__x2apic_send_IPI_dest(dest, vector, apic->dest_logical);
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/*
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* Cluster sibling cpus should be discared now so
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* we would not send IPI them second time.
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*/
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cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr);
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}
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local_irq_restore(flags);
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}
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static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
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}
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static void
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x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
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{
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__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
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}
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static void x2apic_send_IPI_allbutself(int vector)
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{
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__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
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}
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static void x2apic_send_IPI_all(int vector)
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{
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__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
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}
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static int
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x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask,
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unsigned int *apicid)
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{
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u32 dest = 0;
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u16 cluster;
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int i;
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for_each_cpu_and(i, cpumask, andmask) {
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if (!cpumask_test_cpu(i, cpu_online_mask))
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continue;
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dest = per_cpu(x86_cpu_to_logical_apicid, i);
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cluster = x2apic_cluster(i);
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break;
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}
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if (!dest)
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return -EINVAL;
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for_each_cpu_and(i, cpumask, andmask) {
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if (!cpumask_test_cpu(i, cpu_online_mask))
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continue;
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if (cluster != x2apic_cluster(i))
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continue;
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dest |= per_cpu(x86_cpu_to_logical_apicid, i);
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}
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*apicid = dest;
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return 0;
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}
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static void init_x2apic_ldr(void)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR);
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cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, this_cpu));
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for_each_online_cpu(cpu) {
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if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
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continue;
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cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu));
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cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu));
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}
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}
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/*
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* At CPU state changes, update the x2apic cluster sibling info.
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*/
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static int x2apic_prepare_cpu(unsigned int cpu)
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{
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if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL))
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return -ENOMEM;
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if (!zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL)) {
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free_cpumask_var(per_cpu(cpus_in_cluster, cpu));
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return -ENOMEM;
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}
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return 0;
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}
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static int x2apic_dead_cpu(unsigned int this_cpu)
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{
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int cpu;
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for_each_online_cpu(cpu) {
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if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
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continue;
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cpumask_clear_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu));
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cpumask_clear_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu));
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}
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free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
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free_cpumask_var(per_cpu(ipi_mask, this_cpu));
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return 0;
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}
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static int x2apic_cluster_probe(void)
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{
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int cpu = smp_processor_id();
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int ret;
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if (!x2apic_mode)
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return 0;
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ret = cpuhp_setup_state(CPUHP_X2APIC_PREPARE, "X2APIC_PREPARE",
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x2apic_prepare_cpu, x2apic_dead_cpu);
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if (ret < 0) {
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pr_err("Failed to register X2APIC_PREPARE\n");
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return 0;
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}
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cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, cpu));
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return 1;
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}
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static const struct cpumask *x2apic_cluster_target_cpus(void)
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{
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return cpu_all_mask;
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}
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/*
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* Each x2apic cluster is an allocation domain.
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*/
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static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask,
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const struct cpumask *mask)
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{
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/*
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* To minimize vector pressure, default case of boot, device bringup
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* etc will use a single cpu for the interrupt destination.
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*
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* On explicit migration requests coming from irqbalance etc,
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* interrupts will be routed to the x2apic cluster (cluster-id
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* derived from the first cpu in the mask) members specified
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* in the mask.
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*/
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if (mask == x2apic_cluster_target_cpus())
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cpumask_copy(retmask, cpumask_of(cpu));
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else
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cpumask_and(retmask, mask, per_cpu(cpus_in_cluster, cpu));
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}
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static struct apic apic_x2apic_cluster __ro_after_init = {
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.name = "cluster x2apic",
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.probe = x2apic_cluster_probe,
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.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
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.apic_id_valid = x2apic_apic_id_valid,
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.apic_id_registered = x2apic_apic_id_registered,
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.irq_delivery_mode = dest_LowestPrio,
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.irq_dest_mode = 1, /* logical */
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.target_cpus = x2apic_cluster_target_cpus,
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.disable_esr = 0,
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.dest_logical = APIC_DEST_LOGICAL,
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.check_apicid_used = NULL,
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.vector_allocation_domain = cluster_vector_allocation_domain,
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.init_apic_ldr = init_x2apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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.apicid_to_cpu_present = NULL,
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.check_phys_apicid_present = default_check_phys_apicid_present,
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.phys_pkg_id = x2apic_phys_pkg_id,
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.get_apic_id = x2apic_get_apic_id,
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.set_apic_id = x2apic_set_apic_id,
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.cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
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.send_IPI = x2apic_send_IPI,
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.send_IPI_mask = x2apic_send_IPI_mask,
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.send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
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.send_IPI_allbutself = x2apic_send_IPI_allbutself,
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.send_IPI_all = x2apic_send_IPI_all,
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.send_IPI_self = x2apic_send_IPI_self,
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.inquire_remote_apic = NULL,
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.read = native_apic_msr_read,
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.write = native_apic_msr_write,
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.eoi_write = native_apic_msr_eoi_write,
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.icr_read = native_x2apic_icr_read,
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.icr_write = native_x2apic_icr_write,
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.wait_icr_idle = native_x2apic_wait_icr_idle,
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.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
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};
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apic_driver(apic_x2apic_cluster);
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