541 lines
15 KiB
C
541 lines
15 KiB
C
/*
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* Copyright (c) 2010-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include "ath9k.h"
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#include "mci.h"
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static const u8 ath_mci_duty_cycle[] = { 0, 50, 60, 70, 80, 85, 90, 95, 98 };
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static struct ath_mci_profile_info*
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ath_mci_find_profile(struct ath_mci_profile *mci,
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struct ath_mci_profile_info *info)
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{
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struct ath_mci_profile_info *entry;
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list_for_each_entry(entry, &mci->info, list) {
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if (entry->conn_handle == info->conn_handle)
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break;
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}
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return entry;
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}
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static bool ath_mci_add_profile(struct ath_common *common,
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struct ath_mci_profile *mci,
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struct ath_mci_profile_info *info)
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{
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struct ath_mci_profile_info *entry;
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if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
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(info->type == MCI_GPM_COEX_PROFILE_VOICE))
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return false;
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if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
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(info->type != MCI_GPM_COEX_PROFILE_VOICE))
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return false;
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entry = ath_mci_find_profile(mci, info);
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if (entry) {
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memcpy(entry, info, 10);
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} else {
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entry = kzalloc(sizeof(*entry), GFP_KERNEL);
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if (!entry)
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return false;
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memcpy(entry, info, 10);
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INC_PROF(mci, info);
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list_add_tail(&info->list, &mci->info);
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}
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return true;
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}
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static void ath_mci_del_profile(struct ath_common *common,
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struct ath_mci_profile *mci,
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struct ath_mci_profile_info *info)
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{
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struct ath_mci_profile_info *entry;
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entry = ath_mci_find_profile(mci, info);
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if (!entry)
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return;
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DEC_PROF(mci, entry);
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list_del(&entry->list);
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kfree(entry);
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}
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void ath_mci_flush_profile(struct ath_mci_profile *mci)
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{
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struct ath_mci_profile_info *info, *tinfo;
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list_for_each_entry_safe(info, tinfo, &mci->info, list) {
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list_del(&info->list);
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DEC_PROF(mci, info);
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kfree(info);
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}
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mci->aggr_limit = 0;
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}
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static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
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{
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struct ath_mci_profile *mci = &btcoex->mci;
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u32 wlan_airtime = btcoex->btcoex_period *
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(100 - btcoex->duty_cycle) / 100;
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/*
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* Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
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* When wlan_airtime is less than 4ms, aggregation limit has to be
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* adjusted half of wlan_airtime to ensure that the aggregation can fit
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* without collision with BT traffic.
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*/
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if ((wlan_airtime <= 4) &&
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(!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
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mci->aggr_limit = 2 * wlan_airtime;
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}
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static void ath_mci_update_scheme(struct ath_softc *sc)
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{
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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struct ath_btcoex *btcoex = &sc->btcoex;
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struct ath_mci_profile *mci = &btcoex->mci;
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struct ath_mci_profile_info *info;
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u32 num_profile = NUM_PROF(mci);
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if (num_profile == 1) {
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info = list_first_entry(&mci->info,
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struct ath_mci_profile_info,
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list);
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if (mci->num_sco && info->T == 12) {
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mci->aggr_limit = 8;
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ath_dbg(common, MCI,
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"Single SCO, aggregation limit 2 ms\n");
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} else if ((info->type == MCI_GPM_COEX_PROFILE_BNEP) &&
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!info->master) {
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btcoex->btcoex_period = 60;
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ath_dbg(common, MCI,
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"Single slave PAN/FTP, bt period 60 ms\n");
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} else if ((info->type == MCI_GPM_COEX_PROFILE_HID) &&
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(info->T > 0 && info->T < 50) &&
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(info->A > 1 || info->W > 1)) {
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btcoex->duty_cycle = 30;
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mci->aggr_limit = 8;
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ath_dbg(common, MCI,
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"Multiple attempt/timeout single HID "
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"aggregation limit 2 ms dutycycle 30%%\n");
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}
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} else if ((num_profile == 2) && (mci->num_hid == 2)) {
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btcoex->duty_cycle = 30;
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mci->aggr_limit = 8;
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ath_dbg(common, MCI,
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"Two HIDs aggregation limit 2 ms dutycycle 30%%\n");
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} else if (num_profile > 3) {
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mci->aggr_limit = 6;
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ath_dbg(common, MCI,
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"Three or more profiles aggregation limit 1.5 ms\n");
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}
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if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
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if (IS_CHAN_HT(sc->sc_ah->curchan))
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ath_mci_adjust_aggr_limit(btcoex);
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else
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btcoex->btcoex_period >>= 1;
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}
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ath9k_hw_btcoex_disable(sc->sc_ah);
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ath9k_btcoex_timer_pause(sc);
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if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
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return;
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btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_MAX_DUTY_CYCLE : 0);
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if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
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btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
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btcoex->btcoex_period *= 1000;
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btcoex->btcoex_no_stomp = btcoex->btcoex_period *
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(100 - btcoex->duty_cycle) / 100;
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ath9k_hw_btcoex_enable(sc->sc_ah);
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ath9k_btcoex_timer_resume(sc);
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}
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static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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u32 payload[4] = {0, 0, 0, 0};
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switch (opcode) {
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case MCI_GPM_BT_CAL_REQ:
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if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
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ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL);
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ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
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} else {
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ath_dbg(common, MCI, "MCI State mismatch: %d\n",
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ar9003_mci_state(ah, MCI_STATE_BT, NULL));
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}
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break;
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case MCI_GPM_BT_CAL_DONE:
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ar9003_mci_state(ah, MCI_STATE_BT, NULL);
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break;
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case MCI_GPM_BT_CAL_GRANT:
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MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
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ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
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16, false, true);
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break;
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default:
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ath_dbg(common, MCI, "Unknown GPM CAL message\n");
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break;
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}
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}
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static void ath_mci_process_profile(struct ath_softc *sc,
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struct ath_mci_profile_info *info)
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{
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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struct ath_btcoex *btcoex = &sc->btcoex;
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struct ath_mci_profile *mci = &btcoex->mci;
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if (info->start) {
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if (!ath_mci_add_profile(common, mci, info))
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return;
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} else
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ath_mci_del_profile(common, mci, info);
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btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
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mci->aggr_limit = mci->num_sco ? 6 : 0;
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if (NUM_PROF(mci)) {
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btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
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btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
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} else {
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btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
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ATH_BTCOEX_STOMP_LOW;
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btcoex->duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
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}
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ath_mci_update_scheme(sc);
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}
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static void ath_mci_process_status(struct ath_softc *sc,
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struct ath_mci_profile_status *status)
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{
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struct ath_btcoex *btcoex = &sc->btcoex;
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struct ath_mci_profile *mci = &btcoex->mci;
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struct ath_mci_profile_info info;
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int i = 0, old_num_mgmt = mci->num_mgmt;
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/* Link status type are not handled */
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if (status->is_link)
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return;
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memset(&info, 0, sizeof(struct ath_mci_profile_info));
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info.conn_handle = status->conn_handle;
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if (ath_mci_find_profile(mci, &info))
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return;
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if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
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return;
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if (status->is_critical)
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__set_bit(status->conn_handle, mci->status);
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else
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__clear_bit(status->conn_handle, mci->status);
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mci->num_mgmt = 0;
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do {
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if (test_bit(i, mci->status))
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mci->num_mgmt++;
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} while (++i < ATH_MCI_MAX_PROFILE);
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if (old_num_mgmt != mci->num_mgmt)
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ath_mci_update_scheme(sc);
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}
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static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_mci_profile_info profile_info;
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struct ath_mci_profile_status profile_status;
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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u32 version;
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u8 major;
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u8 minor;
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u32 seq_num;
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switch (opcode) {
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case MCI_GPM_COEX_VERSION_QUERY:
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version = ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION,
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NULL);
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break;
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case MCI_GPM_COEX_VERSION_RESPONSE:
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major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
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minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
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version = (major << 8) + minor;
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version = ar9003_mci_state(ah, MCI_STATE_SET_BT_COEX_VERSION,
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&version);
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break;
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case MCI_GPM_COEX_STATUS_QUERY:
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ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_CHANNELS, NULL);
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break;
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case MCI_GPM_COEX_BT_PROFILE_INFO:
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memcpy(&profile_info,
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(rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
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if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
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(profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
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ath_dbg(common, MCI,
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"Illegal profile type = %d, state = %d\n",
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profile_info.type,
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profile_info.start);
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break;
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}
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ath_mci_process_profile(sc, &profile_info);
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break;
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case MCI_GPM_COEX_BT_STATUS_UPDATE:
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profile_status.is_link = *(rx_payload +
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MCI_GPM_COEX_B_STATUS_TYPE);
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profile_status.conn_handle = *(rx_payload +
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MCI_GPM_COEX_B_STATUS_LINKID);
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profile_status.is_critical = *(rx_payload +
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MCI_GPM_COEX_B_STATUS_STATE);
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seq_num = *((u32 *)(rx_payload + 12));
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ath_dbg(common, MCI,
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"BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n",
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profile_status.is_link, profile_status.conn_handle,
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profile_status.is_critical, seq_num);
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ath_mci_process_status(sc, &profile_status);
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break;
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default:
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ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
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break;
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}
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}
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int ath_mci_setup(struct ath_softc *sc)
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{
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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struct ath_mci_coex *mci = &sc->mci_coex;
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struct ath_mci_buf *buf = &mci->sched_buf;
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buf->bf_addr = dma_alloc_coherent(sc->dev,
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ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
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&buf->bf_paddr, GFP_KERNEL);
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if (buf->bf_addr == NULL) {
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ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
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return -ENOMEM;
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}
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memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
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ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
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mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
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mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
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mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
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mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
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ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
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mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
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mci->sched_buf.bf_paddr);
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ath_dbg(common, MCI, "MCI Initialized\n");
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return 0;
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}
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void ath_mci_cleanup(struct ath_softc *sc)
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{
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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struct ath_hw *ah = sc->sc_ah;
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struct ath_mci_coex *mci = &sc->mci_coex;
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struct ath_mci_buf *buf = &mci->sched_buf;
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if (buf->bf_addr)
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dma_free_coherent(sc->dev,
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ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
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buf->bf_addr, buf->bf_paddr);
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ar9003_mci_cleanup(ah);
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ath_dbg(common, MCI, "MCI De-Initialized\n");
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}
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void ath_mci_intr(struct ath_softc *sc)
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{
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struct ath_mci_coex *mci = &sc->mci_coex;
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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u32 mci_int, mci_int_rxmsg;
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u32 offset, subtype, opcode;
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u32 *pgpm;
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u32 more_data = MCI_GPM_MORE;
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bool skip_gpm = false;
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ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
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if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) {
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ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
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return;
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}
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if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
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u32 payload[4] = { 0xffffffff, 0xffffffff,
|
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0xffffffff, 0xffffff00};
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|
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/*
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* The following REMOTE_RESET and SYS_WAKING used to sent
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* only when BT wake up. Now they are always sent, as a
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* recovery method to reset BT MCI's RX alignment.
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*/
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ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
|
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payload, 16, true, false);
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ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
|
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NULL, 0, true, false);
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mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
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ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL);
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|
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/*
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* always do this for recovery and 2G/5G toggling and LNA_TRANS
|
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*/
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ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL);
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}
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|
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if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
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mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
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|
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if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) {
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if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
|
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MCI_BT_SLEEP)
|
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ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE,
|
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NULL);
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}
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}
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|
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if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
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mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
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|
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if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
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|
if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
|
|
MCI_BT_AWAKE)
|
|
ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP,
|
|
NULL);
|
|
}
|
|
}
|
|
|
|
if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
|
|
(mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
|
|
ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL);
|
|
skip_gpm = true;
|
|
}
|
|
|
|
if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
|
|
mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
|
|
offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET,
|
|
NULL);
|
|
}
|
|
|
|
if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
|
|
mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
|
|
|
|
while (more_data == MCI_GPM_MORE) {
|
|
|
|
pgpm = mci->gpm_buf.bf_addr;
|
|
offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
|
|
&more_data);
|
|
|
|
if (offset == MCI_GPM_INVALID)
|
|
break;
|
|
|
|
pgpm += (offset >> 2);
|
|
|
|
/*
|
|
* The first dword is timer.
|
|
* The real data starts from 2nd dword.
|
|
*/
|
|
subtype = MCI_GPM_TYPE(pgpm);
|
|
opcode = MCI_GPM_OPCODE(pgpm);
|
|
|
|
if (skip_gpm)
|
|
goto recycle;
|
|
|
|
if (MCI_GPM_IS_CAL_TYPE(subtype)) {
|
|
ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
|
|
} else {
|
|
switch (subtype) {
|
|
case MCI_GPM_COEX_AGENT:
|
|
ath_mci_msg(sc, opcode, (u8 *)pgpm);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
recycle:
|
|
MCI_GPM_RECYCLE(pgpm);
|
|
}
|
|
}
|
|
|
|
if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
|
|
if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
|
|
mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
|
|
|
|
if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
|
|
mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
|
|
|
|
if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
|
|
int value_dbm = ar9003_mci_state(ah,
|
|
MCI_STATE_CONT_RSSI_POWER, NULL);
|
|
|
|
mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
|
|
|
|
if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL))
|
|
ath_dbg(common, MCI,
|
|
"MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n",
|
|
ar9003_mci_state(ah,
|
|
MCI_STATE_CONT_PRIORITY, NULL),
|
|
value_dbm);
|
|
else
|
|
ath_dbg(common, MCI,
|
|
"MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n",
|
|
ar9003_mci_state(ah,
|
|
MCI_STATE_CONT_PRIORITY, NULL),
|
|
value_dbm);
|
|
}
|
|
|
|
if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
|
|
mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
|
|
|
|
if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
|
|
mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
|
|
}
|
|
|
|
if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
|
|
(mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT))
|
|
mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
|
|
AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
|
|
}
|