266 lines
6.0 KiB
C
266 lines
6.0 KiB
C
/*
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* Renesas Timer Support - OSTM
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*
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* Copyright (C) 2017 Renesas Electronics America, Inc.
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* Copyright (C) 2017 Chris Brandt
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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/*
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* The OSTM contains independent channels.
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* The first OSTM channel probed will be set up as a free running
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* clocksource. Additionally we will use this clocksource for the system
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* schedule timer sched_clock().
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*
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* The second (or more) channel probed will be set up as an interrupt
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* driven clock event.
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*/
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struct ostm_device {
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void __iomem *base;
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unsigned long ticks_per_jiffy;
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struct clock_event_device ced;
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};
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static void __iomem *system_clock; /* For sched_clock() */
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/* OSTM REGISTERS */
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#define OSTM_CMP 0x000 /* RW,32 */
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#define OSTM_CNT 0x004 /* R,32 */
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#define OSTM_TE 0x010 /* R,8 */
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#define OSTM_TS 0x014 /* W,8 */
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#define OSTM_TT 0x018 /* W,8 */
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#define OSTM_CTL 0x020 /* RW,8 */
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#define TE 0x01
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#define TS 0x01
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#define TT 0x01
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#define CTL_PERIODIC 0x00
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#define CTL_ONESHOT 0x02
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#define CTL_FREERUN 0x02
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static struct ostm_device *ced_to_ostm(struct clock_event_device *ced)
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{
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return container_of(ced, struct ostm_device, ced);
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}
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static void ostm_timer_stop(struct ostm_device *ostm)
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{
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if (readb(ostm->base + OSTM_TE) & TE) {
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writeb(TT, ostm->base + OSTM_TT);
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/*
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* Read back the register simply to confirm the write operation
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* has completed since I/O writes can sometimes get queued by
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* the bus architecture.
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*/
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while (readb(ostm->base + OSTM_TE) & TE)
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;
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}
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}
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static int __init ostm_init_clksrc(struct ostm_device *ostm, unsigned long rate)
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{
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/*
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* irq not used (clock sources don't use interrupts)
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*/
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ostm_timer_stop(ostm);
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writel(0, ostm->base + OSTM_CMP);
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writeb(CTL_FREERUN, ostm->base + OSTM_CTL);
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writeb(TS, ostm->base + OSTM_TS);
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return clocksource_mmio_init(ostm->base + OSTM_CNT,
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"ostm", rate,
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300, 32, clocksource_mmio_readl_up);
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}
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static u64 notrace ostm_read_sched_clock(void)
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{
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return readl(system_clock);
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}
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static void __init ostm_init_sched_clock(struct ostm_device *ostm,
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unsigned long rate)
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{
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system_clock = ostm->base + OSTM_CNT;
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sched_clock_register(ostm_read_sched_clock, 32, rate);
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}
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static int ostm_clock_event_next(unsigned long delta,
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struct clock_event_device *ced)
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{
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struct ostm_device *ostm = ced_to_ostm(ced);
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ostm_timer_stop(ostm);
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writel(delta, ostm->base + OSTM_CMP);
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writeb(CTL_ONESHOT, ostm->base + OSTM_CTL);
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writeb(TS, ostm->base + OSTM_TS);
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return 0;
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}
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static int ostm_shutdown(struct clock_event_device *ced)
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{
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struct ostm_device *ostm = ced_to_ostm(ced);
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ostm_timer_stop(ostm);
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return 0;
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}
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static int ostm_set_periodic(struct clock_event_device *ced)
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{
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struct ostm_device *ostm = ced_to_ostm(ced);
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if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
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ostm_timer_stop(ostm);
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writel(ostm->ticks_per_jiffy - 1, ostm->base + OSTM_CMP);
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writeb(CTL_PERIODIC, ostm->base + OSTM_CTL);
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writeb(TS, ostm->base + OSTM_TS);
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return 0;
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}
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static int ostm_set_oneshot(struct clock_event_device *ced)
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{
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struct ostm_device *ostm = ced_to_ostm(ced);
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ostm_timer_stop(ostm);
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return 0;
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}
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static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id)
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{
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struct ostm_device *ostm = dev_id;
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if (clockevent_state_oneshot(&ostm->ced))
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ostm_timer_stop(ostm);
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/* notify clockevent layer */
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if (ostm->ced.event_handler)
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ostm->ced.event_handler(&ostm->ced);
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return IRQ_HANDLED;
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}
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static int __init ostm_init_clkevt(struct ostm_device *ostm, int irq,
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unsigned long rate)
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{
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struct clock_event_device *ced = &ostm->ced;
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int ret = -ENXIO;
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ret = request_irq(irq, ostm_timer_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL,
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"ostm", ostm);
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if (ret) {
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pr_err("ostm: failed to request irq\n");
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return ret;
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}
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ced->name = "ostm";
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ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
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ced->set_state_shutdown = ostm_shutdown;
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ced->set_state_periodic = ostm_set_periodic;
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ced->set_state_oneshot = ostm_set_oneshot;
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ced->set_next_event = ostm_clock_event_next;
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ced->shift = 32;
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ced->rating = 300;
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ced->cpumask = cpumask_of(0);
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clockevents_config_and_register(ced, rate, 0xf, 0xffffffff);
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return 0;
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}
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static int __init ostm_init(struct device_node *np)
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{
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struct ostm_device *ostm;
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int ret = -EFAULT;
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struct clk *ostm_clk = NULL;
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int irq;
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unsigned long rate;
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ostm = kzalloc(sizeof(*ostm), GFP_KERNEL);
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if (!ostm)
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return -ENOMEM;
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ostm->base = of_iomap(np, 0);
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if (!ostm->base) {
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pr_err("ostm: failed to remap I/O memory\n");
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goto err;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (irq < 0) {
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pr_err("ostm: Failed to get irq\n");
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goto err;
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}
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ostm_clk = of_clk_get(np, 0);
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if (IS_ERR(ostm_clk)) {
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pr_err("ostm: Failed to get clock\n");
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ostm_clk = NULL;
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goto err;
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}
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ret = clk_prepare_enable(ostm_clk);
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if (ret) {
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pr_err("ostm: Failed to enable clock\n");
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goto err;
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}
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rate = clk_get_rate(ostm_clk);
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ostm->ticks_per_jiffy = (rate + HZ / 2) / HZ;
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/*
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* First probed device will be used as system clocksource. Any
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* additional devices will be used as clock events.
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*/
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if (!system_clock) {
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ret = ostm_init_clksrc(ostm, rate);
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if (!ret) {
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ostm_init_sched_clock(ostm, rate);
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pr_info("ostm: used for clocksource\n");
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}
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} else {
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ret = ostm_init_clkevt(ostm, irq, rate);
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if (!ret)
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pr_info("ostm: used for clock events\n");
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}
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err:
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if (ret) {
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clk_disable_unprepare(ostm_clk);
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iounmap(ostm->base);
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kfree(ostm);
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return ret;
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}
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return 0;
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}
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TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
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