254 lines
7.1 KiB
C
254 lines
7.1 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "hwmgr.h"
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#include "cz_clockpowergating.h"
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#include "cz_ppsmc.h"
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/* PhyID -> Status Mapping in DDI_PHY_GEN_STATUS
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0 GFX0L (3:0), (27:24),
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1 GFX0H (7:4), (31:28),
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2 GFX1L (3:0), (19:16),
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3 GFX1H (7:4), (23:20),
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4 DDIL (3:0), (11: 8),
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5 DDIH (7:4), (15:12),
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6 DDI2L (3:0), ( 3: 0),
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7 DDI2H (7:4), ( 7: 4),
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*/
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#define DDI_PHY_GEN_STATUS_VAL(phyID) (1 << ((3 - ((phyID & 0x07)/2))*8 + (phyID & 0x01)*4))
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#define IS_PHY_ID_USED_BY_PLL(PhyID) (((0xF3 & (1 << PhyID)) & 0xFF) ? true : false)
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int cz_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating)
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{
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int ret = 0;
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switch (block) {
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case PHM_AsicBlock_UVD_MVC:
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case PHM_AsicBlock_UVD:
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case PHM_AsicBlock_UVD_HD:
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case PHM_AsicBlock_UVD_SD:
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if (gating == PHM_ClockGateSetting_StaticOff)
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ret = cz_dpm_powerdown_uvd(hwmgr);
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else
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ret = cz_dpm_powerup_uvd(hwmgr);
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break;
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case PHM_AsicBlock_GFX:
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default:
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break;
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}
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return ret;
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}
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bool cz_phm_is_safe_for_asic_block(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, enum PHM_AsicBlock block)
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{
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return true;
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}
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int cz_phm_enable_disable_gfx_power_gating(struct pp_hwmgr *hwmgr, bool enable)
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{
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return 0;
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}
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int cz_phm_smu_power_up_down_pcie(struct pp_hwmgr *hwmgr, uint32_t target, bool up, uint32_t args)
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{
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/* TODO */
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return 0;
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}
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int cz_phm_initialize_display_phy_access(struct pp_hwmgr *hwmgr, bool initialize, bool accesshw)
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{
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/* TODO */
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return 0;
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}
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int cz_phm_get_display_phy_access_info(struct pp_hwmgr *hwmgr)
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{
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/* TODO */
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return 0;
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}
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int cz_phm_gate_unused_display_phys(struct pp_hwmgr *hwmgr)
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{
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/* TODO */
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return 0;
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}
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int cz_phm_ungate_all_display_phys(struct pp_hwmgr *hwmgr)
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{
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/* TODO */
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return 0;
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}
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static int cz_tf_uvd_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
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{
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return 0;
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}
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static int cz_tf_vce_power_gating_initialize(struct pp_hwmgr *hwmgr, void *pInput, void *pOutput, void *pStorage, int Result)
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{
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return 0;
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}
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int cz_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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uint32_t dpm_features = 0;
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if (enable &&
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phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDDPM)) {
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cz_hwmgr->dpm_flags |= DPMFlags_UVD_Enabled;
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dpm_features |= UVD_DPM_MASK;
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
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} else {
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dpm_features |= UVD_DPM_MASK;
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cz_hwmgr->dpm_flags &= ~DPMFlags_UVD_Enabled;
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
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}
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return 0;
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}
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int cz_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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uint32_t dpm_features = 0;
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if (enable && phm_cap_enabled(
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hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_VCEDPM)) {
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cz_hwmgr->dpm_flags |= DPMFlags_VCE_Enabled;
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dpm_features |= VCE_DPM_MASK;
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_EnableAllSmuFeatures, dpm_features);
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} else {
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dpm_features |= VCE_DPM_MASK;
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cz_hwmgr->dpm_flags &= ~DPMFlags_VCE_Enabled;
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_DisableAllSmuFeatures, dpm_features);
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}
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return 0;
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}
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int cz_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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if (cz_hwmgr->uvd_power_gated == bgate)
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return 0;
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cz_hwmgr->uvd_power_gated = bgate;
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if (bgate) {
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_GATE);
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cgs_set_powergating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_GATE);
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cz_dpm_update_uvd_dpm(hwmgr, true);
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cz_dpm_powerdown_uvd(hwmgr);
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} else {
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cz_dpm_powerup_uvd(hwmgr);
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cgs_set_powergating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_UNGATE);
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_UNGATE);
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cz_dpm_update_uvd_dpm(hwmgr, false);
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}
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return 0;
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}
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int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_VCEPowerGating)) {
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if (cz_hwmgr->vce_power_gated != bgate) {
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if (bgate) {
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cgs_set_clockgating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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cgs_set_powergating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_GATE);
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cz_enable_disable_vce_dpm(hwmgr, false);
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cz_dpm_powerdown_vce(hwmgr);
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cz_hwmgr->vce_power_gated = true;
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} else {
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cz_dpm_powerup_vce(hwmgr);
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cz_hwmgr->vce_power_gated = false;
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cgs_set_powergating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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cgs_set_clockgating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_GATE);
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cz_dpm_update_vce_dpm(hwmgr);
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cz_enable_disable_vce_dpm(hwmgr, true);
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return 0;
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}
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}
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} else {
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cz_hwmgr->vce_power_gated = bgate;
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cz_dpm_update_vce_dpm(hwmgr);
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cz_enable_disable_vce_dpm(hwmgr, !bgate);
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return 0;
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}
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if (!cz_hwmgr->vce_power_gated)
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cz_dpm_update_vce_dpm(hwmgr);
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return 0;
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}
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static const struct phm_master_table_item cz_enable_clock_power_gatings_list[] = {
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/*we don't need an exit table here, because there is only D3 cold on Kv*/
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{ phm_cf_want_uvd_power_gating, cz_tf_uvd_power_gating_initialize },
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{ phm_cf_want_vce_power_gating, cz_tf_vce_power_gating_initialize },
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/* to do { NULL, cz_tf_xdma_power_gating_enable }, */
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{ NULL, NULL }
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};
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const struct phm_master_table_header cz_phm_enable_clock_power_gatings_master = {
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0,
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PHM_MasterTableFlag_None,
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cz_enable_clock_power_gatings_list
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};
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