300 lines
7.2 KiB
C
300 lines
7.2 KiB
C
/*
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* drivers/clocksource/timer-oxnas-rps.c
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*
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* Copyright (C) 2009 Oxford Semiconductor Ltd
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* Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
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* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/clockchips.h>
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#include <linux/sched_clock.h>
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/* TIMER1 used as tick
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* TIMER2 used as clocksource
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*/
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/* Registers definitions */
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#define TIMER_LOAD_REG 0x0
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#define TIMER_CURR_REG 0x4
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#define TIMER_CTRL_REG 0x8
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#define TIMER_CLRINT_REG 0xC
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#define TIMER_BITS 24
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#define TIMER_MAX_VAL (BIT(TIMER_BITS) - 1)
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#define TIMER_PERIODIC BIT(6)
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#define TIMER_ENABLE BIT(7)
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#define TIMER_DIV1 (0)
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#define TIMER_DIV16 (1 << 2)
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#define TIMER_DIV256 (2 << 2)
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#define TIMER1_REG_OFFSET 0
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#define TIMER2_REG_OFFSET 0x20
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/* Clockevent & Clocksource data */
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struct oxnas_rps_timer {
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struct clock_event_device clkevent;
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void __iomem *clksrc_base;
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void __iomem *clkevt_base;
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unsigned long timer_period;
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unsigned int timer_prescaler;
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struct clk *clk;
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int irq;
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};
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static irqreturn_t oxnas_rps_timer_irq(int irq, void *dev_id)
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{
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struct oxnas_rps_timer *rps = dev_id;
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writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
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rps->clkevent.event_handler(&rps->clkevent);
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return IRQ_HANDLED;
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}
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static void oxnas_rps_timer_config(struct oxnas_rps_timer *rps,
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unsigned long period,
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unsigned int periodic)
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{
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uint32_t cfg = rps->timer_prescaler;
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if (period)
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cfg |= TIMER_ENABLE;
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if (periodic)
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cfg |= TIMER_PERIODIC;
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writel_relaxed(period, rps->clkevt_base + TIMER_LOAD_REG);
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writel_relaxed(cfg, rps->clkevt_base + TIMER_CTRL_REG);
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}
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static int oxnas_rps_timer_shutdown(struct clock_event_device *evt)
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{
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struct oxnas_rps_timer *rps =
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container_of(evt, struct oxnas_rps_timer, clkevent);
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oxnas_rps_timer_config(rps, 0, 0);
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return 0;
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}
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static int oxnas_rps_timer_set_periodic(struct clock_event_device *evt)
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{
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struct oxnas_rps_timer *rps =
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container_of(evt, struct oxnas_rps_timer, clkevent);
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oxnas_rps_timer_config(rps, rps->timer_period, 1);
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return 0;
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}
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static int oxnas_rps_timer_set_oneshot(struct clock_event_device *evt)
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{
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struct oxnas_rps_timer *rps =
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container_of(evt, struct oxnas_rps_timer, clkevent);
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oxnas_rps_timer_config(rps, rps->timer_period, 0);
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return 0;
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}
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static int oxnas_rps_timer_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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struct oxnas_rps_timer *rps =
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container_of(evt, struct oxnas_rps_timer, clkevent);
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oxnas_rps_timer_config(rps, delta, 0);
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return 0;
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}
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static int __init oxnas_rps_clockevent_init(struct oxnas_rps_timer *rps)
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{
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ulong clk_rate = clk_get_rate(rps->clk);
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ulong timer_rate;
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/* Start with prescaler 1 */
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rps->timer_prescaler = TIMER_DIV1;
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rps->timer_period = DIV_ROUND_UP(clk_rate, HZ);
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timer_rate = clk_rate;
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if (rps->timer_period > TIMER_MAX_VAL) {
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rps->timer_prescaler = TIMER_DIV16;
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timer_rate = clk_rate / 16;
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rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
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}
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if (rps->timer_period > TIMER_MAX_VAL) {
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rps->timer_prescaler = TIMER_DIV256;
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timer_rate = clk_rate / 256;
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rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
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}
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rps->clkevent.name = "oxnas-rps";
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rps->clkevent.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ;
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rps->clkevent.tick_resume = oxnas_rps_timer_shutdown;
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rps->clkevent.set_state_shutdown = oxnas_rps_timer_shutdown;
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rps->clkevent.set_state_periodic = oxnas_rps_timer_set_periodic;
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rps->clkevent.set_state_oneshot = oxnas_rps_timer_set_oneshot;
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rps->clkevent.set_next_event = oxnas_rps_timer_next_event;
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rps->clkevent.rating = 200;
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rps->clkevent.cpumask = cpu_possible_mask;
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rps->clkevent.irq = rps->irq;
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clockevents_config_and_register(&rps->clkevent,
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timer_rate,
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1,
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TIMER_MAX_VAL);
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pr_info("Registered clock event rate %luHz prescaler %x period %lu\n",
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clk_rate,
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rps->timer_prescaler,
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rps->timer_period);
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return 0;
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}
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/* Clocksource */
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static void __iomem *timer_sched_base;
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static u64 notrace oxnas_rps_read_sched_clock(void)
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{
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return ~readl_relaxed(timer_sched_base);
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}
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static int __init oxnas_rps_clocksource_init(struct oxnas_rps_timer *rps)
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{
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ulong clk_rate = clk_get_rate(rps->clk);
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int ret;
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/* use prescale 16 */
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clk_rate = clk_rate / 16;
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writel_relaxed(TIMER_MAX_VAL, rps->clksrc_base + TIMER_LOAD_REG);
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writel_relaxed(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16,
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rps->clksrc_base + TIMER_CTRL_REG);
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timer_sched_base = rps->clksrc_base + TIMER_CURR_REG;
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sched_clock_register(oxnas_rps_read_sched_clock,
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TIMER_BITS, clk_rate);
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ret = clocksource_mmio_init(timer_sched_base,
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"oxnas_rps_clocksource_timer",
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clk_rate, 250, TIMER_BITS,
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clocksource_mmio_readl_down);
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if (WARN_ON(ret)) {
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pr_err("can't register clocksource\n");
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return ret;
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}
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pr_info("Registered clocksource rate %luHz\n", clk_rate);
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return 0;
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}
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static int __init oxnas_rps_timer_init(struct device_node *np)
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{
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struct oxnas_rps_timer *rps;
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void __iomem *base;
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int ret;
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rps = kzalloc(sizeof(*rps), GFP_KERNEL);
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if (!rps)
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return -ENOMEM;
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rps->clk = of_clk_get(np, 0);
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if (IS_ERR(rps->clk)) {
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ret = PTR_ERR(rps->clk);
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goto err_alloc;
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}
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ret = clk_prepare_enable(rps->clk);
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if (ret)
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goto err_clk;
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base = of_iomap(np, 0);
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if (!base) {
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ret = -ENXIO;
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goto err_clk_prepare;
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}
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rps->irq = irq_of_parse_and_map(np, 0);
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if (rps->irq < 0) {
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ret = -EINVAL;
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goto err_iomap;
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}
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rps->clkevt_base = base + TIMER1_REG_OFFSET;
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rps->clksrc_base = base + TIMER2_REG_OFFSET;
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/* Disable timers */
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writel_relaxed(0, rps->clkevt_base + TIMER_CTRL_REG);
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writel_relaxed(0, rps->clksrc_base + TIMER_CTRL_REG);
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writel_relaxed(0, rps->clkevt_base + TIMER_LOAD_REG);
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writel_relaxed(0, rps->clksrc_base + TIMER_LOAD_REG);
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writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
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writel_relaxed(0, rps->clksrc_base + TIMER_CLRINT_REG);
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ret = request_irq(rps->irq, oxnas_rps_timer_irq,
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IRQF_TIMER | IRQF_IRQPOLL,
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"rps-timer", rps);
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if (ret)
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goto err_iomap;
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ret = oxnas_rps_clocksource_init(rps);
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if (ret)
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goto err_irqreq;
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ret = oxnas_rps_clockevent_init(rps);
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if (ret)
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goto err_irqreq;
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return 0;
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err_irqreq:
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free_irq(rps->irq, rps);
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err_iomap:
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iounmap(base);
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err_clk_prepare:
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clk_disable_unprepare(rps->clk);
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err_clk:
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clk_put(rps->clk);
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err_alloc:
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kfree(rps);
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return ret;
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}
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CLOCKSOURCE_OF_DECLARE(ox810se_rps,
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"oxsemi,ox810se-rps-timer", oxnas_rps_timer_init);
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CLOCKSOURCE_OF_DECLARE(ox820_rps,
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"oxsemi,ox820se-rps-timer", oxnas_rps_timer_init);
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