172 lines
5.1 KiB
C
172 lines
5.1 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ahennessy@mvista.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/txx9/generic.h>
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#include <asm/txx9/jmr3927.h>
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#if JMR3927_IRQ_END > NR_IRQS
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#error JMR3927_IRQ_END > NR_IRQS
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#endif
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static unsigned char irc_level[TX3927_NUM_IR] = {
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5, 5, 5, 5, 5, 5, /* INT[5:0] */
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7, 7, /* SIO */
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5, 5, 5, 0, 0, /* DMA, PIO, PCI */
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6, 6, 6 /* TMR */
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};
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/*
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* CP0_STATUS is a thread's resource (saved/restored on context switch).
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* So disable_irq/enable_irq MUST handle IOC/IRC registers.
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*/
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static void mask_irq_ioc(unsigned int irq)
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{
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/* 0: mask */
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unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
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unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
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unsigned int bit = 1 << irq_nr;
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jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
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/* flush write buffer */
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(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
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}
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static void unmask_irq_ioc(unsigned int irq)
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{
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/* 0: mask */
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unsigned int irq_nr = irq - JMR3927_IRQ_IOC;
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unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
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unsigned int bit = 1 << irq_nr;
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jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
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/* flush write buffer */
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(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
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}
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static int jmr3927_ioc_irqroute(void)
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{
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unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
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int i;
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for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
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if (istat & (1 << i))
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return JMR3927_IRQ_IOC + i;
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}
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return -1;
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}
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static int jmr3927_irq_dispatch(int pending)
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{
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int irq;
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if ((pending & CAUSEF_IP7) == 0)
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return -1;
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irq = (pending >> CAUSEB_IP2) & 0x0f;
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irq += JMR3927_IRQ_IRC;
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if (irq == JMR3927_IRQ_IOCINT)
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irq = jmr3927_ioc_irqroute();
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return irq;
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}
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#ifdef CONFIG_PCI
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static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
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{
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printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
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printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
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tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
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return IRQ_HANDLED;
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}
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static struct irqaction pcierr_action = {
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.handler = jmr3927_pcierr_interrupt,
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.mask = CPU_MASK_NONE,
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.name = "PCI error",
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};
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#endif
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static void __init jmr3927_irq_init(void);
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void __init jmr3927_irq_setup(void)
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{
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txx9_irq_dispatch = jmr3927_irq_dispatch;
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/* Now, interrupt control disabled, */
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/* all IRC interrupts are masked, */
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/* all IRC interrupt mode are Low Active. */
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/* mask all IOC interrupts */
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jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
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/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
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jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
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/* clear PCI Soft interrupts */
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jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
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/* clear PCI Reset interrupts */
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jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
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jmr3927_irq_init();
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/* setup IOC interrupt 1 (PCI, MODEM) */
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set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
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#ifdef CONFIG_PCI
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setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
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#endif
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/* enable all CPU interrupt bits. */
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set_c0_status(ST0_IM); /* IE bit is still 0. */
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}
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static struct irq_chip jmr3927_irq_ioc = {
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.name = "jmr3927_ioc",
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.ack = mask_irq_ioc,
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.mask = mask_irq_ioc,
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.mask_ack = mask_irq_ioc,
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.unmask = unmask_irq_ioc,
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};
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static void __init jmr3927_irq_init(void)
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{
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u32 i;
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txx9_irq_init(TX3927_IRC_REG);
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for (i = 0; i < TXx9_MAX_IR; i++)
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txx9_irq_set_pri(i, irc_level[i]);
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for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
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set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
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}
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