648 lines
14 KiB
C
648 lines
14 KiB
C
/*
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* Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
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*
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* Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
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*
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* Adapted from mac_scsinew.c:
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*/
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/*
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* Generic Macintosh NCR5380 driver
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*
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* Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
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*
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* derived in part from:
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*/
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/*
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* Generic Generic NCR5380 driver
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*
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* Copyright 1995, Russell King
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*
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* ALPHA RELEASE 1.
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*
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* For more information, please consult
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*
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* NCR 5380 Family
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* SCSI Protocol Controller
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* Databook
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*
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* NCR Microelectronics
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* 1635 Aeroplaza Drive
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* Colorado Springs, CO 80916
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* 1+ (719) 578-3400
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* 1+ (800) 334-5454
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*/
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/*
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* This is from mac_scsi.h, but hey, maybe this is useful for Sun3 too! :)
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*
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* Options :
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*
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* PARITY - enable parity checking. Not supported.
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*
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* SCSI2 - enable support for SCSI-II tagged queueing. Untested.
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*
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* USLEEP - enable support for devices that don't disconnect. Untested.
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*/
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/*
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* $Log: sun3_NCR5380.c,v $
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*/
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#define AUTOSENSE
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#include <linux/types.h>
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#include <linux/stddef.h>
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#include <linux/ctype.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <asm/io.h>
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#include <asm/sun3ints.h>
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#include <asm/dvma.h>
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#include <asm/idprom.h>
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#include <asm/machines.h>
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#define NDEBUG 0
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#define NDEBUG_ABORT 0x00100000
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#define NDEBUG_TAGS 0x00200000
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#define NDEBUG_MERGING 0x00400000
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/* dma on! */
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#define REAL_DMA
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#include "scsi.h"
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#include "initio.h"
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#include <scsi/scsi_host.h>
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#include "sun3_scsi.h"
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static void NCR5380_print(struct Scsi_Host *instance);
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/* #define OLDDMA */
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#define USE_WRAPPER
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/*#define RESET_BOOT */
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#define DRIVER_SETUP
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/*
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* BUG can be used to trigger a strange code-size related hang on 2.1 kernels
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*/
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#ifdef BUG
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#undef RESET_BOOT
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#undef DRIVER_SETUP
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#endif
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/* #define SUPPORT_TAGS */
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#define ENABLE_IRQ() enable_irq( IRQ_SUN3_SCSI );
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static irqreturn_t scsi_sun3_intr(int irq, void *dummy);
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static inline unsigned char sun3scsi_read(int reg);
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static inline void sun3scsi_write(int reg, int value);
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static int setup_can_queue = -1;
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module_param(setup_can_queue, int, 0);
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static int setup_cmd_per_lun = -1;
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module_param(setup_cmd_per_lun, int, 0);
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static int setup_sg_tablesize = -1;
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module_param(setup_sg_tablesize, int, 0);
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#ifdef SUPPORT_TAGS
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static int setup_use_tagged_queuing = -1;
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module_param(setup_use_tagged_queuing, int, 0);
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#endif
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static int setup_hostid = -1;
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module_param(setup_hostid, int, 0);
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static struct scsi_cmnd *sun3_dma_setup_done = NULL;
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#define AFTER_RESET_DELAY (HZ/2)
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/* ms to wait after hitting dma regs */
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#define SUN3_DMA_DELAY 10
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/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
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#define SUN3_DVMA_BUFSIZE 0xe000
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/* minimum number of bytes to do dma on */
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#define SUN3_DMA_MINSIZE 128
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static volatile unsigned char *sun3_scsi_regp;
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static volatile struct sun3_dma_regs *dregs;
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#ifdef OLDDMA
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static unsigned char *dmabuf = NULL; /* dma memory buffer */
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#endif
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static struct sun3_udc_regs *udc_regs = NULL;
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static unsigned char *sun3_dma_orig_addr = NULL;
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static unsigned long sun3_dma_orig_count = 0;
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static int sun3_dma_active = 0;
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static unsigned long last_residual = 0;
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/*
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* NCR 5380 register access functions
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*/
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static inline unsigned char sun3scsi_read(int reg)
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{
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return( sun3_scsi_regp[reg] );
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}
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static inline void sun3scsi_write(int reg, int value)
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{
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sun3_scsi_regp[reg] = value;
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}
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/* dma controller register access functions */
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static inline unsigned short sun3_udc_read(unsigned char reg)
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{
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unsigned short ret;
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dregs->udc_addr = UDC_CSR;
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udelay(SUN3_DMA_DELAY);
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ret = dregs->udc_data;
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udelay(SUN3_DMA_DELAY);
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return ret;
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}
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static inline void sun3_udc_write(unsigned short val, unsigned char reg)
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{
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dregs->udc_addr = reg;
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udelay(SUN3_DMA_DELAY);
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dregs->udc_data = val;
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udelay(SUN3_DMA_DELAY);
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}
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/*
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* XXX: status debug
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*/
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static struct Scsi_Host *default_instance;
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/*
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* Function : int sun3scsi_detect(struct scsi_host_template * tpnt)
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*
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* Purpose : initializes mac NCR5380 driver based on the
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* command line / compile time port and irq definitions.
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*
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* Inputs : tpnt - template for this SCSI adapter.
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*
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* Returns : 1 if a host adapter was found, 0 if not.
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*
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*/
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int __init sun3scsi_detect(struct scsi_host_template * tpnt)
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{
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unsigned long ioaddr;
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static int called = 0;
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struct Scsi_Host *instance;
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/* check that this machine has an onboard 5380 */
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switch(idprom->id_machtype) {
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case SM_SUN3|SM_3_50:
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case SM_SUN3|SM_3_60:
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break;
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default:
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return 0;
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}
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if(called)
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return 0;
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tpnt->proc_name = "Sun3 5380 SCSI";
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/* setup variables */
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tpnt->can_queue =
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(setup_can_queue > 0) ? setup_can_queue : CAN_QUEUE;
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tpnt->cmd_per_lun =
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(setup_cmd_per_lun > 0) ? setup_cmd_per_lun : CMD_PER_LUN;
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tpnt->sg_tablesize =
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(setup_sg_tablesize >= 0) ? setup_sg_tablesize : SG_TABLESIZE;
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if (setup_hostid >= 0)
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tpnt->this_id = setup_hostid;
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else {
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/* use 7 as default */
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tpnt->this_id = 7;
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}
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ioaddr = (unsigned long)ioremap(IOBASE_SUN3_SCSI, PAGE_SIZE);
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sun3_scsi_regp = (unsigned char *)ioaddr;
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dregs = (struct sun3_dma_regs *)(((unsigned char *)ioaddr) + 8);
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if((udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs)))
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== NULL) {
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printk("SUN3 Scsi couldn't allocate DVMA memory!\n");
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return 0;
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}
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#ifdef OLDDMA
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if((dmabuf = dvma_malloc_align(SUN3_DVMA_BUFSIZE, 0x10000)) == NULL) {
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printk("SUN3 Scsi couldn't allocate DVMA memory!\n");
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return 0;
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}
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#endif
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#ifdef SUPPORT_TAGS
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if (setup_use_tagged_queuing < 0)
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setup_use_tagged_queuing = USE_TAGGED_QUEUING;
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#endif
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instance = scsi_register (tpnt, sizeof(struct NCR5380_hostdata));
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if(instance == NULL)
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return 0;
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default_instance = instance;
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instance->io_port = (unsigned long) ioaddr;
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instance->irq = IRQ_SUN3_SCSI;
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NCR5380_init(instance, 0);
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instance->n_io_port = 32;
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((struct NCR5380_hostdata *)instance->hostdata)->ctrl = 0;
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if (request_irq(instance->irq, scsi_sun3_intr,
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0, "Sun3SCSI-5380", instance)) {
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#ifndef REAL_DMA
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printk("scsi%d: IRQ%d not free, interrupts disabled\n",
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instance->host_no, instance->irq);
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instance->irq = SCSI_IRQ_NONE;
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#else
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printk("scsi%d: IRQ%d not free, bailing out\n",
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instance->host_no, instance->irq);
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return 0;
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#endif
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}
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printk("scsi%d: Sun3 5380 at port %lX irq", instance->host_no, instance->io_port);
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if (instance->irq == SCSI_IRQ_NONE)
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printk ("s disabled");
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else
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printk (" %d", instance->irq);
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printk(" options CAN_QUEUE=%d CMD_PER_LUN=%d release=%d",
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instance->can_queue, instance->cmd_per_lun,
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SUN3SCSI_PUBLIC_RELEASE);
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printk("\nscsi%d:", instance->host_no);
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NCR5380_print_options(instance);
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printk("\n");
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dregs->csr = 0;
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udelay(SUN3_DMA_DELAY);
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dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
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udelay(SUN3_DMA_DELAY);
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dregs->fifo_count = 0;
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called = 1;
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#ifdef RESET_BOOT
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sun3_scsi_reset_boot(instance);
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#endif
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return 1;
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}
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int sun3scsi_release (struct Scsi_Host *shpnt)
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{
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if (shpnt->irq != SCSI_IRQ_NONE)
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free_irq(shpnt->irq, shpnt);
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iounmap((void *)sun3_scsi_regp);
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NCR5380_exit(shpnt);
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return 0;
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}
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#ifdef RESET_BOOT
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/*
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* Our 'bus reset on boot' function
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*/
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static void sun3_scsi_reset_boot(struct Scsi_Host *instance)
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{
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unsigned long end;
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NCR5380_local_declare();
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NCR5380_setup(instance);
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/*
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* Do a SCSI reset to clean up the bus during initialization. No
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* messing with the queues, interrupts, or locks necessary here.
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*/
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printk( "Sun3 SCSI: resetting the SCSI bus..." );
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/* switch off SCSI IRQ - catch an interrupt without IRQ bit set else */
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// sun3_disable_irq( IRQ_SUN3_SCSI );
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/* get in phase */
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NCR5380_write( TARGET_COMMAND_REG,
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PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
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/* assert RST */
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NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
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/* The min. reset hold time is 25us, so 40us should be enough */
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udelay( 50 );
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/* reset RST and interrupt */
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NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
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NCR5380_read( RESET_PARITY_INTERRUPT_REG );
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for( end = jiffies + AFTER_RESET_DELAY; time_before(jiffies, end); )
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barrier();
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/* switch on SCSI IRQ again */
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// sun3_enable_irq( IRQ_SUN3_SCSI );
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printk( " done\n" );
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}
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#endif
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const char * sun3scsi_info (struct Scsi_Host *spnt) {
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return "";
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}
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// safe bits for the CSR
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#define CSR_GOOD 0x060f
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static irqreturn_t scsi_sun3_intr(int irq, void *dummy)
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{
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unsigned short csr = dregs->csr;
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int handled = 0;
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if(csr & ~CSR_GOOD) {
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if(csr & CSR_DMA_BUSERR) {
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printk("scsi%d: bus error in dma\n", default_instance->host_no);
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}
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if(csr & CSR_DMA_CONFLICT) {
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printk("scsi%d: dma conflict\n", default_instance->host_no);
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}
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handled = 1;
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}
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if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
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NCR5380_intr(irq, dummy);
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handled = 1;
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}
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return IRQ_RETVAL(handled);
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}
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/*
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* Debug stuff - to be called on NMI, or sysrq key. Use at your own risk;
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* reentering NCR5380_print_status seems to have ugly side effects
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*/
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/* this doesn't seem to get used at all -- sam */
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#if 0
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void sun3_sun3_debug (void)
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{
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unsigned long flags;
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NCR5380_local_declare();
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if (default_instance) {
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local_irq_save(flags);
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NCR5380_print_status(default_instance);
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local_irq_restore(flags);
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}
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}
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#endif
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/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
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static unsigned long sun3scsi_dma_setup(void *data, unsigned long count, int write_flag)
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{
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#ifdef OLDDMA
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if(write_flag)
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memcpy(dmabuf, data, count);
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else {
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sun3_dma_orig_addr = data;
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sun3_dma_orig_count = count;
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}
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#else
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void *addr;
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if(sun3_dma_orig_addr != NULL)
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dvma_unmap(sun3_dma_orig_addr);
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// addr = sun3_dvma_page((unsigned long)data, (unsigned long)dmabuf);
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addr = (void *)dvma_map((unsigned long) data, count);
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sun3_dma_orig_addr = addr;
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sun3_dma_orig_count = count;
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#endif
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dregs->fifo_count = 0;
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sun3_udc_write(UDC_RESET, UDC_CSR);
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/* reset fifo */
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dregs->csr &= ~CSR_FIFO;
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dregs->csr |= CSR_FIFO;
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/* set direction */
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if(write_flag)
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dregs->csr |= CSR_SEND;
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else
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dregs->csr &= ~CSR_SEND;
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/* byte count for fifo */
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dregs->fifo_count = count;
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sun3_udc_write(UDC_RESET, UDC_CSR);
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/* reset fifo */
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dregs->csr &= ~CSR_FIFO;
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dregs->csr |= CSR_FIFO;
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if(dregs->fifo_count != count) {
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printk("scsi%d: fifo_mismatch %04x not %04x\n",
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default_instance->host_no, dregs->fifo_count,
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(unsigned int) count);
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NCR5380_print(default_instance);
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}
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/* setup udc */
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#ifdef OLDDMA
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udc_regs->addr_hi = ((dvma_vtob(dmabuf) & 0xff0000) >> 8);
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udc_regs->addr_lo = (dvma_vtob(dmabuf) & 0xffff);
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#else
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udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
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udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
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#endif
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udc_regs->count = count/2; /* count in words */
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udc_regs->mode_hi = UDC_MODE_HIWORD;
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if(write_flag) {
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if(count & 1)
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udc_regs->count++;
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udc_regs->mode_lo = UDC_MODE_LSEND;
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udc_regs->rsel = UDC_RSEL_SEND;
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} else {
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udc_regs->mode_lo = UDC_MODE_LRECV;
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udc_regs->rsel = UDC_RSEL_RECV;
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}
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/* announce location of regs block */
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sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
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UDC_CHN_HI);
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sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
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/* set dma master on */
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sun3_udc_write(0xd, UDC_MODE);
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/* interrupt enable */
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sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
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return count;
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}
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static inline unsigned long sun3scsi_dma_count(struct Scsi_Host *instance)
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{
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unsigned short resid;
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dregs->udc_addr = 0x32;
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udelay(SUN3_DMA_DELAY);
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resid = dregs->udc_data;
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udelay(SUN3_DMA_DELAY);
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resid *= 2;
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return (unsigned long) resid;
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}
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static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance)
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{
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return last_residual;
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}
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static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted,
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struct scsi_cmnd *cmd,
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int write_flag)
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{
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if (cmd->request->cmd_type == REQ_TYPE_FS)
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return wanted;
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else
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return 0;
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}
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static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
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{
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sun3_udc_write(UDC_CHN_START, UDC_CSR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* clean up after our dma is done */
|
|
static int sun3scsi_dma_finish(int write_flag)
|
|
{
|
|
unsigned short count;
|
|
unsigned short fifo;
|
|
int ret = 0;
|
|
|
|
sun3_dma_active = 0;
|
|
#if 1
|
|
// check to empty the fifo on a read
|
|
if(!write_flag) {
|
|
int tmo = 20000; /* .2 sec */
|
|
|
|
while(1) {
|
|
if(dregs->csr & CSR_FIFO_EMPTY)
|
|
break;
|
|
|
|
if(--tmo <= 0) {
|
|
printk("sun3scsi: fifo failed to empty!\n");
|
|
return 1;
|
|
}
|
|
udelay(10);
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
count = sun3scsi_dma_count(default_instance);
|
|
#ifdef OLDDMA
|
|
|
|
/* if we've finished a read, copy out the data we read */
|
|
if(sun3_dma_orig_addr) {
|
|
/* check for residual bytes after dma end */
|
|
if(count && (NCR5380_read(BUS_AND_STATUS_REG) &
|
|
(BASR_PHASE_MATCH | BASR_ACK))) {
|
|
printk("scsi%d: sun3_scsi_finish: read overrun baby... ", default_instance->host_no);
|
|
printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG));
|
|
ret = count;
|
|
}
|
|
|
|
/* copy in what we dma'd no matter what */
|
|
memcpy(sun3_dma_orig_addr, dmabuf, sun3_dma_orig_count);
|
|
sun3_dma_orig_addr = NULL;
|
|
|
|
}
|
|
#else
|
|
|
|
fifo = dregs->fifo_count;
|
|
last_residual = fifo;
|
|
|
|
/* empty bytes from the fifo which didn't make it */
|
|
if((!write_flag) && (count - fifo) == 2) {
|
|
unsigned short data;
|
|
unsigned char *vaddr;
|
|
|
|
data = dregs->fifo_data;
|
|
vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
|
|
|
|
vaddr += (sun3_dma_orig_count - fifo);
|
|
|
|
vaddr[-2] = (data & 0xff00) >> 8;
|
|
vaddr[-1] = (data & 0xff);
|
|
}
|
|
|
|
dvma_unmap(sun3_dma_orig_addr);
|
|
sun3_dma_orig_addr = NULL;
|
|
#endif
|
|
sun3_udc_write(UDC_RESET, UDC_CSR);
|
|
dregs->fifo_count = 0;
|
|
dregs->csr &= ~CSR_SEND;
|
|
|
|
/* reset fifo */
|
|
dregs->csr &= ~CSR_FIFO;
|
|
dregs->csr |= CSR_FIFO;
|
|
|
|
sun3_dma_setup_done = NULL;
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#include "sun3_NCR5380.c"
|
|
|
|
static struct scsi_host_template driver_template = {
|
|
.show_info = sun3scsi_show_info,
|
|
.name = SUN3_SCSI_NAME,
|
|
.detect = sun3scsi_detect,
|
|
.release = sun3scsi_release,
|
|
.info = sun3scsi_info,
|
|
.queuecommand = sun3scsi_queue_command,
|
|
.eh_abort_handler = sun3scsi_abort,
|
|
.eh_bus_reset_handler = sun3scsi_bus_reset,
|
|
.can_queue = CAN_QUEUE,
|
|
.this_id = 7,
|
|
.sg_tablesize = SG_TABLESIZE,
|
|
.cmd_per_lun = CMD_PER_LUN,
|
|
.use_clustering = DISABLE_CLUSTERING
|
|
};
|
|
|
|
|
|
#include "scsi_module.c"
|
|
|
|
MODULE_LICENSE("GPL");
|