286 lines
9.0 KiB
C
286 lines
9.0 KiB
C
/*
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* Samsung EXYNOS SoC series PCIe PHY driver
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*
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* Phy provider for PCIe controller on Exynos SoC series
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*
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* Copyright (C) 2017 Samsung Electronics Co., Ltd.
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* Jaehoon Chung <jh80.chung@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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/* PCIe Purple registers */
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#define PCIE_PHY_GLOBAL_RESET 0x000
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#define PCIE_PHY_COMMON_RESET 0x004
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#define PCIE_PHY_CMN_REG 0x008
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#define PCIE_PHY_MAC_RESET 0x00c
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#define PCIE_PHY_PLL_LOCKED 0x010
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#define PCIE_PHY_TRSVREG_RESET 0x020
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#define PCIE_PHY_TRSV_RESET 0x024
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/* PCIe PHY registers */
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#define PCIE_PHY_IMPEDANCE 0x004
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#define PCIE_PHY_PLL_DIV_0 0x008
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#define PCIE_PHY_PLL_BIAS 0x00c
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#define PCIE_PHY_DCC_FEEDBACK 0x014
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#define PCIE_PHY_PLL_DIV_1 0x05c
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#define PCIE_PHY_COMMON_POWER 0x064
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#define PCIE_PHY_COMMON_PD_CMN BIT(3)
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#define PCIE_PHY_TRSV0_EMP_LVL 0x084
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#define PCIE_PHY_TRSV0_DRV_LVL 0x088
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#define PCIE_PHY_TRSV0_RXCDR 0x0ac
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#define PCIE_PHY_TRSV0_POWER 0x0c4
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#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
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#define PCIE_PHY_TRSV0_LVCC 0x0dc
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#define PCIE_PHY_TRSV1_EMP_LVL 0x144
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#define PCIE_PHY_TRSV1_RXCDR 0x16c
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#define PCIE_PHY_TRSV1_POWER 0x184
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#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
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#define PCIE_PHY_TRSV1_LVCC 0x19c
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#define PCIE_PHY_TRSV2_EMP_LVL 0x204
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#define PCIE_PHY_TRSV2_RXCDR 0x22c
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#define PCIE_PHY_TRSV2_POWER 0x244
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#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
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#define PCIE_PHY_TRSV2_LVCC 0x25c
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#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
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#define PCIE_PHY_TRSV3_RXCDR 0x2ec
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#define PCIE_PHY_TRSV3_POWER 0x304
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#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
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#define PCIE_PHY_TRSV3_LVCC 0x31c
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struct exynos_pcie_phy_data {
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const struct phy_ops *ops;
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};
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/* For Exynos pcie phy */
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struct exynos_pcie_phy {
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const struct exynos_pcie_phy_data *drv_data;
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void __iomem *phy_base;
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void __iomem *blk_base; /* For exynos5440 */
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};
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static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
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{
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writel(val, base + offset);
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}
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static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
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{
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return readl(base + offset);
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}
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/* For Exynos5440 specific functions */
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static int exynos5440_pcie_phy_init(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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/* DCC feedback control off */
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exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
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/* set TX/RX impedance */
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exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
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/* set 50Mhz PHY clock */
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exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
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exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
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/* set TX Differential output for lane 0 */
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exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
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/* set TX Pre-emphasis Level Control for lane 0 to minimum */
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exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
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/* set RX clock and data recovery bandwidth */
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exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
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exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
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exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
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exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
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exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
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/* change TX Pre-emphasis Level Control for lanes */
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exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
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exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
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exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
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exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
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/* set LVCC */
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exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
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exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
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exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
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exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
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/* pulse for common reset */
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exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
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udelay(500);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
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return 0;
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}
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static int exynos5440_pcie_phy_power_on(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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u32 val;
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
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val &= ~PCIE_PHY_COMMON_PD_CMN;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
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val &= ~PCIE_PHY_TRSV0_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
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val &= ~PCIE_PHY_TRSV1_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
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val &= ~PCIE_PHY_TRSV2_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
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val &= ~PCIE_PHY_TRSV3_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
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return 0;
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}
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static int exynos5440_pcie_phy_power_off(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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u32 val;
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if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
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(val != 0), 1, 500)) {
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dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
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return -ETIMEDOUT;
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}
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
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val |= PCIE_PHY_COMMON_PD_CMN;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
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val |= PCIE_PHY_TRSV0_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
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val |= PCIE_PHY_TRSV1_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
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val |= PCIE_PHY_TRSV2_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
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val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
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val |= PCIE_PHY_TRSV3_PD_TSV;
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exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
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return 0;
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}
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static int exynos5440_pcie_phy_reset(struct phy *phy)
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{
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struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
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exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
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exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
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return 0;
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}
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static const struct phy_ops exynos5440_phy_ops = {
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.init = exynos5440_pcie_phy_init,
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.power_on = exynos5440_pcie_phy_power_on,
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.power_off = exynos5440_pcie_phy_power_off,
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.reset = exynos5440_pcie_phy_reset,
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.owner = THIS_MODULE,
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};
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static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
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.ops = &exynos5440_phy_ops,
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};
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static const struct of_device_id exynos_pcie_phy_match[] = {
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{
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.compatible = "samsung,exynos5440-pcie-phy",
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.data = &exynos5440_pcie_phy_data,
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
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static int exynos_pcie_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct exynos_pcie_phy *exynos_phy;
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struct phy *generic_phy;
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struct phy_provider *phy_provider;
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struct resource *res;
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const struct exynos_pcie_phy_data *drv_data;
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drv_data = of_device_get_match_data(dev);
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if (!drv_data)
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return -ENODEV;
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exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
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if (!exynos_phy)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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exynos_phy->phy_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(exynos_phy->phy_base))
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return PTR_ERR(exynos_phy->phy_base);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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exynos_phy->blk_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(exynos_phy->blk_base))
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return PTR_ERR(exynos_phy->blk_base);
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exynos_phy->drv_data = drv_data;
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generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
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if (IS_ERR(generic_phy)) {
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dev_err(dev, "failed to create PHY\n");
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return PTR_ERR(generic_phy);
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}
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phy_set_drvdata(generic_phy, exynos_phy);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static struct platform_driver exynos_pcie_phy_driver = {
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.probe = exynos_pcie_phy_probe,
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.driver = {
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.of_match_table = exynos_pcie_phy_match,
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.name = "exynos_pcie_phy",
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}
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};
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module_platform_driver(exynos_pcie_phy_driver);
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MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC PCIe PHY driver");
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MODULE_AUTHOR("Jaehoon Chung <jh80.chung@samsung.com>");
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MODULE_LICENSE("GPL v2");
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