269 lines
6.5 KiB
C
269 lines
6.5 KiB
C
/*
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* rcar_du_lvdsenc.c -- R-Car Display Unit LVDS Encoder
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*
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* Copyright (C) 2013-2014 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "rcar_du_drv.h"
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#include "rcar_du_encoder.h"
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#include "rcar_du_lvdsenc.h"
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#include "rcar_lvds_regs.h"
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struct rcar_du_lvdsenc {
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struct rcar_du_device *dev;
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unsigned int index;
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void __iomem *mmio;
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struct clk *clock;
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bool enabled;
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enum rcar_lvds_input input;
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enum rcar_lvds_mode mode;
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};
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static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data)
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{
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iowrite32(data, lvds->mmio + reg);
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}
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static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds,
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struct rcar_du_crtc *rcrtc)
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{
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const struct drm_display_mode *mode = &rcrtc->crtc.mode;
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unsigned int freq = mode->clock;
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u32 lvdcr0;
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u32 pllcr;
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/* PLL clock configuration */
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if (freq < 39000)
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pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
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else if (freq < 61000)
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pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
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else if (freq < 121000)
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pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
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else
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pllcr = LVDPLLCR_PLLDLYCNT_150M;
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rcar_lvds_write(lvds, LVDPLLCR, pllcr);
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/* Select the input, hardcode mode 0, enable LVDS operation and turn
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* bias circuitry on.
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*/
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lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_BEN | LVDCR0_LVEN;
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if (rcrtc->index == 2)
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lvdcr0 |= LVDCR0_DUSEL;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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/* Turn all the channels on. */
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rcar_lvds_write(lvds, LVDCR1,
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LVDCR1_CHSTBY_GEN2(3) | LVDCR1_CHSTBY_GEN2(2) |
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LVDCR1_CHSTBY_GEN2(1) | LVDCR1_CHSTBY_GEN2(0) |
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LVDCR1_CLKSTBY_GEN2);
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/* Turn the PLL on, wait for the startup delay, and turn the output
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* on.
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*/
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lvdcr0 |= LVDCR0_PLLON;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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usleep_range(100, 150);
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lvdcr0 |= LVDCR0_LVRES;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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}
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static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
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struct rcar_du_crtc *rcrtc)
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{
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const struct drm_display_mode *mode = &rcrtc->crtc.mode;
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unsigned int freq = mode->clock;
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u32 lvdcr0;
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u32 pllcr;
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/* PLL clock configuration */
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if (freq < 42000)
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pllcr = LVDPLLCR_PLLDIVCNT_42M;
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else if (freq < 85000)
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pllcr = LVDPLLCR_PLLDIVCNT_85M;
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else if (freq < 128000)
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pllcr = LVDPLLCR_PLLDIVCNT_128M;
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else
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pllcr = LVDPLLCR_PLLDIVCNT_148M;
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rcar_lvds_write(lvds, LVDPLLCR, pllcr);
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/* Turn all the channels on. */
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rcar_lvds_write(lvds, LVDCR1,
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LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
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LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |
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LVDCR1_CLKSTBY_GEN3);
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/*
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* Turn the PLL on, set it to LVDS normal mode, wait for the startup
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* delay and turn the output on.
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*/
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lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_PLLON;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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lvdcr0 |= LVDCR0_PWD;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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usleep_range(100, 150);
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lvdcr0 |= LVDCR0_LVRES;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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}
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static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
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struct rcar_du_crtc *rcrtc)
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{
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u32 lvdhcr;
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int ret;
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if (lvds->enabled)
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return 0;
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ret = clk_prepare_enable(lvds->clock);
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if (ret < 0)
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return ret;
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/* Hardcode the channels and control signals routing for now.
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*
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* HSYNC -> CTRL0
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* VSYNC -> CTRL1
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* DISP -> CTRL2
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* 0 -> CTRL3
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*/
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rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
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LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
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LVDCTRCR_CTR0SEL_HSYNC);
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if (rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES))
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lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
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| LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
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else
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lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
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| LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
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rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
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/* Perform generation-specific initialization. */
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if (lvds->dev->info->gen < 3)
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rcar_du_lvdsenc_start_gen2(lvds, rcrtc);
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else
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rcar_du_lvdsenc_start_gen3(lvds, rcrtc);
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lvds->enabled = true;
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return 0;
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}
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static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds)
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{
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if (!lvds->enabled)
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return;
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rcar_lvds_write(lvds, LVDCR0, 0);
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rcar_lvds_write(lvds, LVDCR1, 0);
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clk_disable_unprepare(lvds->clock);
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lvds->enabled = false;
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}
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int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc,
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bool enable)
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{
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if (!enable) {
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rcar_du_lvdsenc_stop(lvds);
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return 0;
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} else if (crtc) {
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struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
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return rcar_du_lvdsenc_start(lvds, rcrtc);
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} else
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return -EINVAL;
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}
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void rcar_du_lvdsenc_atomic_check(struct rcar_du_lvdsenc *lvds,
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struct drm_display_mode *mode)
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{
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struct rcar_du_device *rcdu = lvds->dev;
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/* The internal LVDS encoder has a restricted clock frequency operating
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* range (30MHz to 150MHz on Gen2, 25.175MHz to 148.5MHz on Gen3). Clamp
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* the clock accordingly.
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*/
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if (rcdu->info->gen < 3)
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mode->clock = clamp(mode->clock, 30000, 150000);
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else
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mode->clock = clamp(mode->clock, 25175, 148500);
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}
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void rcar_du_lvdsenc_set_mode(struct rcar_du_lvdsenc *lvds,
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enum rcar_lvds_mode mode)
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{
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lvds->mode = mode;
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}
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static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds,
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struct platform_device *pdev)
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{
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struct resource *mem;
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char name[7];
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sprintf(name, "lvds.%u", lvds->index);
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mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(lvds->mmio))
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return PTR_ERR(lvds->mmio);
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lvds->clock = devm_clk_get(&pdev->dev, name);
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if (IS_ERR(lvds->clock)) {
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dev_err(&pdev->dev, "failed to get clock for %s\n", name);
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return PTR_ERR(lvds->clock);
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}
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return 0;
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}
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int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
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{
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struct platform_device *pdev = to_platform_device(rcdu->dev);
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struct rcar_du_lvdsenc *lvds;
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unsigned int i;
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int ret;
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for (i = 0; i < rcdu->info->num_lvds; ++i) {
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lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
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if (lvds == NULL)
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return -ENOMEM;
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lvds->dev = rcdu;
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lvds->index = i;
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lvds->input = i ? RCAR_LVDS_INPUT_DU1 : RCAR_LVDS_INPUT_DU0;
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lvds->enabled = false;
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ret = rcar_du_lvdsenc_get_resources(lvds, pdev);
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if (ret < 0)
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return ret;
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rcdu->lvds[i] = lvds;
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}
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return 0;
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}
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