592 lines
14 KiB
Plaintext
592 lines
14 KiB
Plaintext
/*
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* Copyright 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/gpio/meson8b-gpio.h>
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#include <dt-bindings/reset/amlogic,meson8b-reset.h>
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#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
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#include "meson.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x200>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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};
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cpu1: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x201>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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};
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cpu2: cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x202>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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};
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cpu3: cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x203>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
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operating-points-v2 = <&cpu_opp_table>;
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clocks = <&clkc CLKID_CPUCLK>;
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};
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};
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-96000000 {
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opp-hz = /bits/ 64 <96000000>;
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opp-microvolt = <860000>;
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};
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opp-192000000 {
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opp-hz = /bits/ 64 <192000000>;
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opp-microvolt = <860000>;
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};
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opp-312000000 {
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opp-hz = /bits/ 64 <312000000>;
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opp-microvolt = <860000>;
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <860000>;
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};
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opp-504000000 {
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opp-hz = /bits/ 64 <504000000>;
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opp-microvolt = <860000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <860000>;
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};
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opp-720000000 {
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opp-hz = /bits/ 64 <720000000>;
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opp-microvolt = <860000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <900000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1140000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1140000>;
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};
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opp-1320000000 {
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opp-hz = /bits/ 64 <1320000000>;
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opp-microvolt = <1140000>;
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};
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opp-1488000000 {
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opp-hz = /bits/ 64 <1488000000>;
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opp-microvolt = <1140000>;
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};
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opp-1536000000 {
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opp-hz = /bits/ 64 <1536000000>;
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opp-microvolt = <1140000>;
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};
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};
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gpu_opp_table: gpu-opp-table {
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compatible = "operating-points-v2";
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opp-255000000 {
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opp-hz = /bits/ 64 <255000000>;
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opp-microvolt = <1150000>;
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};
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opp-364300000 {
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opp-hz = /bits/ 64 <364300000>;
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opp-microvolt = <1150000>;
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};
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opp-425000000 {
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opp-hz = /bits/ 64 <425000000>;
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opp-microvolt = <1150000>;
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};
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opp-510000000 {
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opp-hz = /bits/ 64 <510000000>;
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opp-microvolt = <1150000>;
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};
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opp-637500000 {
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opp-hz = /bits/ 64 <637500000>;
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opp-microvolt = <1150000>;
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turbo-mode;
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};
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};
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pmu {
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compatible = "arm,cortex-a5-pmu";
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* 2 MiB reserved for Hardware ROM Firmware? */
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hwrom@0 {
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reg = <0x0 0x200000>;
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no-map;
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};
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};
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apb: bus@d0000000 {
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compatible = "simple-bus";
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reg = <0xd0000000 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xd0000000 0x200000>;
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mali: gpu@c0000 {
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compatible = "amlogic,meson8b-mali", "arm,mali-450";
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reg = <0xc0000 0x40000>;
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interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gp", "gpmmu", "pp", "pmu",
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"pp0", "ppmmu0", "pp1", "ppmmu1";
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resets = <&reset RESET_MALI>;
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
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clock-names = "bus", "core";
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operating-points-v2 = <&gpu_opp_table>;
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switch-delay = <0xffff>;
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};
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};
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}; /* end of / */
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&aobus {
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pmu: pmu@e0 {
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compatible = "amlogic,meson8b-pmu", "syscon";
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reg = <0xe0 0x18>;
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};
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pinctrl_aobus: pinctrl@84 {
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compatible = "amlogic,meson8b-aobus-pinctrl";
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reg = <0x84 0xc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio_ao: ao-bank@14 {
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reg = <0x14 0x4>,
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<0x2c 0x4>,
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<0x24 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 16>;
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};
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uart_ao_a_pins: uart_ao_a {
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mux {
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groups = "uart_tx_ao_a", "uart_rx_ao_a";
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function = "uart_ao";
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bias-disable;
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};
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};
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ir_recv_pins: remote {
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mux {
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groups = "remote_input";
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function = "remote";
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bias-disable;
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};
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};
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};
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};
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&cbus {
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reset: reset-controller@4404 {
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compatible = "amlogic,meson8b-reset";
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reg = <0x4404 0x9c>;
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#reset-cells = <1>;
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};
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analog_top: analog-top@81a8 {
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compatible = "amlogic,meson8b-analog-top", "syscon";
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reg = <0x81a8 0x14>;
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};
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pwm_ef: pwm@86c0 {
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compatible = "amlogic,meson8b-pwm";
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reg = <0x86c0 0x10>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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clock-measure@8758 {
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compatible = "amlogic,meson8b-clk-measure";
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reg = <0x8758 0x1c>;
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};
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pinctrl_cbus: pinctrl@9880 {
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compatible = "amlogic,meson8b-cbus-pinctrl";
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reg = <0x9880 0x10>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio: banks@80b0 {
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reg = <0x80b0 0x28>,
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<0x80e8 0x18>,
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<0x8120 0x18>,
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<0x8030 0x38>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_cbus 0 0 83>;
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};
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eth_rgmii_pins: eth-rgmii {
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mux {
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groups = "eth_tx_clk",
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"eth_tx_en",
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"eth_txd1_0",
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"eth_txd0_0",
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"eth_rx_clk",
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"eth_rx_dv",
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"eth_rxd1",
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"eth_rxd0",
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"eth_mdio_en",
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"eth_mdc",
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"eth_ref_clk",
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"eth_txd2",
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"eth_txd3",
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"eth_rxd3",
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"eth_rxd2";
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function = "ethernet";
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bias-disable;
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};
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};
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eth_rmii_pins: eth-rmii {
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mux {
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groups = "eth_tx_en",
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"eth_txd1_0",
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"eth_txd0_0",
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"eth_rx_clk",
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"eth_rx_dv",
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"eth_rxd1",
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"eth_rxd0",
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"eth_mdio_en",
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"eth_mdc";
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function = "ethernet";
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bias-disable;
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};
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};
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i2c_a_pins: i2c-a {
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mux {
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groups = "i2c_sda_a", "i2c_sck_a";
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function = "i2c_a";
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bias-disable;
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};
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};
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sd_b_pins: sd-b {
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mux {
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groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
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"sd_d3_b", "sd_clk_b", "sd_cmd_b";
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function = "sd_b";
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bias-disable;
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};
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};
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pwm_c1_pins: pwm-c1 {
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mux {
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groups = "pwm_c1";
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function = "pwm_c";
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bias-disable;
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};
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};
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uart_b0_pins: uart-b0 {
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mux {
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groups = "uart_tx_b0",
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"uart_rx_b0";
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function = "uart_b";
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bias-disable;
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};
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};
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uart_b0_cts_rts_pins: uart-b0-cts-rts {
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mux {
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groups = "uart_cts_b0",
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"uart_rts_b0";
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function = "uart_b";
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bias-disable;
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};
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};
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};
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};
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&ahb_sram {
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smp-sram@1ff80 {
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compatible = "amlogic,meson8b-smp-sram";
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reg = <0x1ff80 0x8>;
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};
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};
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&efuse {
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compatible = "amlogic,meson8b-efuse";
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clocks = <&clkc CLKID_EFUSE>;
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clock-names = "core";
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temperature_calib: calib@1f4 {
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/* only the upper two bytes are relevant */
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reg = <0x1f4 0x4>;
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};
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};
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ðmac {
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compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
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reg = <0xc9410000 0x10000
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0xc1108140 0x4>;
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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resets = <&reset RESET_ETHERNET>;
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reset-names = "stmmaceth";
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};
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&gpio_intc {
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compatible = "amlogic,meson-gpio-intc",
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"amlogic,meson8b-gpio-intc";
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status = "okay";
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};
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&hhi {
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clkc: clock-controller {
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compatible = "amlogic,meson8-clkc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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&hwrng {
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compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
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clocks = <&clkc CLKID_RNG0>;
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clock-names = "core";
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};
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&i2c_AO {
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clocks = <&clkc CLKID_CLK81>;
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};
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&i2c_A {
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clocks = <&clkc CLKID_I2C>;
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};
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&i2c_B {
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clocks = <&clkc CLKID_I2C>;
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};
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&L2 {
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arm,data-latency = <3 3 3>;
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arm,tag-latency = <2 2 2>;
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arm,filter-ranges = <0x100000 0xc0000000>;
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prefetch-data = <1>;
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prefetch-instr = <1>;
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arm,shared-override;
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};
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&periph {
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scu@0 {
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compatible = "arm,cortex-a5-scu";
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reg = <0x0 0x100>;
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};
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timer@200 {
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compatible = "arm,cortex-a5-global-timer";
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reg = <0x200 0x20>;
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interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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clocks = <&clkc CLKID_PERIPH>;
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/*
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* the arm_global_timer driver currently does not handle clock
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* rate changes. Keep it disabled for now.
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*/
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status = "disabled";
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};
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timer@600 {
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compatible = "arm,cortex-a5-twd-timer";
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reg = <0x600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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clocks = <&clkc CLKID_PERIPH>;
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};
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};
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&pwm_ab {
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compatible = "amlogic,meson8b-pwm";
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};
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&pwm_cd {
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compatible = "amlogic,meson8b-pwm";
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};
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&rtc {
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compatible = "amlogic,meson8b-rtc";
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resets = <&reset RESET_RTC>;
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};
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&saradc {
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compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
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clocks = <&clkc CLKID_XTAL>,
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<&clkc CLKID_SAR_ADC>;
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clock-names = "clkin", "core";
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amlogic,hhi-sysctrl = <&hhi>;
|
|
nvmem-cells = <&temperature_calib>;
|
|
nvmem-cell-names = "temperature_calib";
|
|
};
|
|
|
|
&sdio {
|
|
compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
|
|
clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
|
|
clock-names = "core", "clkin";
|
|
};
|
|
|
|
&timer_abcde {
|
|
clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
|
|
clock-names = "xtal", "pclk";
|
|
};
|
|
|
|
&uart_AO {
|
|
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
|
|
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
|
|
clock-names = "baud", "xtal", "pclk";
|
|
};
|
|
|
|
&uart_A {
|
|
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
|
|
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
|
|
clock-names = "baud", "xtal", "pclk";
|
|
};
|
|
|
|
&uart_B {
|
|
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
|
|
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
|
|
clock-names = "baud", "xtal", "pclk";
|
|
};
|
|
|
|
&uart_C {
|
|
compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
|
|
clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
|
|
clock-names = "baud", "xtal", "pclk";
|
|
};
|
|
|
|
&usb0 {
|
|
compatible = "amlogic,meson8b-usb", "snps,dwc2";
|
|
clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
|
|
clock-names = "otg";
|
|
};
|
|
|
|
&usb1 {
|
|
compatible = "amlogic,meson8b-usb", "snps,dwc2";
|
|
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
|
clock-names = "otg";
|
|
};
|
|
|
|
&usb0_phy {
|
|
compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
|
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
|
|
clock-names = "usb_general", "usb";
|
|
resets = <&reset RESET_USB_OTG>;
|
|
};
|
|
|
|
&usb1_phy {
|
|
compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
|
|
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
|
|
clock-names = "usb_general", "usb";
|
|
resets = <&reset RESET_USB_OTG>;
|
|
};
|
|
|
|
&wdt {
|
|
compatible = "amlogic,meson8b-wdt";
|
|
};
|