96 lines
2.0 KiB
Plaintext
96 lines
2.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
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*
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* Copyright (c) 2017, Microchip Technology Inc.
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* 2017 Cristian Birsan <cristian.birsan@microchip.com>
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* 2017 Claudiu Beznea <claudiu.beznea@microchip.com>
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*/
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#include "sama5d2.dtsi"
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#include "sama5d2-pinfunc.h"
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/ {
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model = "Atmel SAMA5D27 SoM1";
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compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
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clocks {
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slow_xtal {
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clock-frequency = <32768>;
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};
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main_xtal {
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clock-frequency = <24000000>;
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};
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};
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ahb {
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apb {
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qspi1: spi@f0024000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi1_default>;
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <80000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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m25p,fast-read;
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};
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};
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macb0: ethernet@f8008000 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb0_default>;
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phy-mode = "rmii";
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ethernet-phy@0 {
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reg = <0x0>;
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interrupt-parent = <&pioA>;
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interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_macb0_phy_irq>;
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};
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};
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pinctrl@fc038000 {
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pinctrl_qspi1_default: qspi1_default {
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sck_cs {
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pinmux = <PIN_PB5__QSPI1_SCK>,
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<PIN_PB6__QSPI1_CS>;
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bias-disable;
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};
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data {
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pinmux = <PIN_PB7__QSPI1_IO0>,
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<PIN_PB8__QSPI1_IO1>,
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<PIN_PB9__QSPI1_IO2>,
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<PIN_PB10__QSPI1_IO3>;
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bias-pull-up;
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};
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};
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pinctrl_macb0_default: macb0_default {
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pinmux = <PIN_PD9__GTXCK>,
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<PIN_PD10__GTXEN>,
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<PIN_PD11__GRXDV>,
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<PIN_PD12__GRXER>,
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<PIN_PD13__GRX0>,
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<PIN_PD14__GRX1>,
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<PIN_PD15__GTX0>,
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<PIN_PD16__GTX1>,
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<PIN_PD17__GMDC>,
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<PIN_PD18__GMDIO>;
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bias-disable;
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};
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pinctrl_macb0_phy_irq: macb0_phy_irq {
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pinmux = <PIN_PD31__GPIO>;
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bias-disable;
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};
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};
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};
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};
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};
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