67 lines
1.6 KiB
Plaintext
67 lines
1.6 KiB
Plaintext
Qualcomm SuperSpeed DWC3 USB SoC controller
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Required properties:
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- compatible: should contain "qcom,dwc3"
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- clocks: A list of phandle + clock-specifier pairs for the
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clocks listed in clock-names
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- clock-names: Should contain the following:
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"core" Master/Core clock, have to be >= 125 MHz for SS
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operation and >= 60MHz for HS operation
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Optional clocks:
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"iface" System bus AXI clock. Not present on all platforms
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"sleep" Sleep clock, used when USB3 core goes into low
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power mode (U3).
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Required child node:
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A child node must exist to represent the core DWC3 IP block. The name of
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the node is not important. The content of the node is defined in dwc3.txt.
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Phy documentation is provided in the following places:
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Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
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Example device nodes:
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hs_phy: phy@100f8800 {
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compatible = "qcom,dwc3-hs-usb-phy";
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reg = <0x100f8800 0x30>;
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clocks = <&gcc USB30_0_UTMI_CLK>;
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clock-names = "ref";
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#phy-cells = <0>;
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status = "ok";
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};
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ss_phy: phy@100f8830 {
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compatible = "qcom,dwc3-ss-usb-phy";
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reg = <0x100f8830 0x30>;
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clocks = <&gcc USB30_0_MASTER_CLK>;
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clock-names = "ref";
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#phy-cells = <0>;
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status = "ok";
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};
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usb3_0: usb30@0 {
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compatible = "qcom,dwc3";
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&gcc USB30_0_MASTER_CLK>;
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clock-names = "core";
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ranges;
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status = "ok";
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dwc3@10000000 {
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compatible = "snps,dwc3";
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reg = <0x10000000 0xcd00>;
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interrupts = <0 205 0x4>;
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phys = <&hs_phy>, <&ss_phy>;
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phy-names = "usb2-phy", "usb3-phy";
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tx-fifo-resize;
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dr_mode = "host";
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};
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};
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