30 lines
939 B
Plaintext
30 lines
939 B
Plaintext
* Renesas RZ Clock Pulse Generator (CPG)
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The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
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CPU and GPU clocks, and several fixed ratio dividers.
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Required Properties:
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- compatible: Must be one of
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- "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
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- "renesas,rz-cpg-clocks" for the generic RZ CPG
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: References to possible parent clocks. Order must match clock modes
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in the datasheet. For the r7s72100, this is extal, usb_x1.
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "pll",
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"i", and "g"
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Example
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-------
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cpg_clocks: cpg_clocks@fcfe0000 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-cpg-clocks",
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"renesas,rz-cpg-clocks";
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reg = <0xfcfe0000 0x18>;
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clocks = <&extal_clk>, <&usb_x1_clk>;
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clock-output-names = "pll", "i", "g";
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};
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