179 lines
4.5 KiB
Plaintext
179 lines
4.5 KiB
Plaintext
* Gated Clock bindings for Marvell EBU SoCs
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Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
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peripheral clocks to be gated to save some power. The clock consumer
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should specify the desired clock by having the clock ID in its
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"clocks" phandle cell. The clock ID is directly mapped to the
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corresponding clock gating control bit in HW to ease manual clock
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lookup in datasheet.
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The following is a list of provided IDs for Armada 370:
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ID Clock Peripheral
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-----------------------------------
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0 Audio AC97 Cntrl
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1 pex0_en PCIe 0 Clock out
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2 pex1_en PCIe 1 Clock out
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3 ge1 Gigabit Ethernet 1
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4 ge0 Gigabit Ethernet 0
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5 pex0 PCIe Cntrl 0
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9 pex1 PCIe Cntrl 1
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15 sata0 SATA Host 0
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17 sdio SDHCI Host
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25 tdm Time Division Mplx
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28 ddr DDR Cntrl
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30 sata1 SATA Host 0
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The following is a list of provided IDs for Armada 375:
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ID Clock Peripheral
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-----------------------------------
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2 mu Management Unit
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3 pp Packet Processor
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4 ptp PTP
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5 pex0 PCIe 0 Clock out
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6 pex1 PCIe 1 Clock out
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8 audio Audio Cntrl
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11 nd_clk Nand Flash Cntrl
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14 sata0_link SATA 0 Link
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15 sata0_core SATA 0 Core
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16 usb3 USB3 Host
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17 sdio SDHCI Host
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18 usb USB Host
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19 gop Gigabit Ethernet MAC
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20 sata1_link SATA 1 Link
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21 sata1_core SATA 1 Core
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22 xor0 XOR DMA 0
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23 xor1 XOR DMA 0
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24 copro Coprocessor
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25 tdm Time Division Mplx
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28 crypto0_enc Cryptographic Unit Port 0 Encryption
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29 crypto0_core Cryptographic Unit Port 0 Core
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30 crypto1_enc Cryptographic Unit Port 1 Encryption
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31 crypto1_core Cryptographic Unit Port 1 Core
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The following is a list of provided IDs for Armada 380/385:
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ID Clock Peripheral
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-----------------------------------
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0 audio Audio
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2 ge2 Gigabit Ethernet 2
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3 ge1 Gigabit Ethernet 1
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4 ge0 Gigabit Ethernet 0
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5 pex1 PCIe 1
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6 pex2 PCIe 2
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7 pex3 PCIe 3
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8 pex0 PCIe 0
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9 usb3h0 USB3 Host 0
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10 usb3h1 USB3 Host 1
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11 usb3d USB3 Device
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13 bm Buffer Management
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14 crypto0z Cryptographic 0 Z
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15 sata0 SATA 0
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16 crypto1z Cryptographic 1 Z
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17 sdio SDIO
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18 usb2 USB 2
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21 crypto1 Cryptographic 1
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22 xor0 XOR 0
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23 crypto0 Cryptographic 0
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25 tdm Time Division Multiplexing
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28 xor1 XOR 1
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30 sata1 SATA 1
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The following is a list of provided IDs for Armada XP:
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ID Clock Peripheral
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-----------------------------------
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0 audio Audio Cntrl
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1 ge3 Gigabit Ethernet 3
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2 ge2 Gigabit Ethernet 2
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3 ge1 Gigabit Ethernet 1
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4 ge0 Gigabit Ethernet 0
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5 pex0 PCIe Cntrl 0
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6 pex1 PCIe Cntrl 1
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7 pex2 PCIe Cntrl 2
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8 pex3 PCIe Cntrl 3
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13 bp
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14 sata0lnk
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15 sata0 SATA Host 0
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16 lcd LCD Cntrl
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17 sdio SDHCI Host
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18 usb0 USB Host 0
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19 usb1 USB Host 1
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20 usb2 USB Host 2
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22 xor0 XOR DMA 0
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23 crypto CESA engine
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25 tdm Time Division Mplx
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28 xor1 XOR DMA 1
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29 sata1lnk
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30 sata1 SATA Host 0
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The following is a list of provided IDs for Dove:
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ID Clock Peripheral
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-----------------------------------
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0 usb0 USB Host 0
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1 usb1 USB Host 1
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2 ge Gigabit Ethernet
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3 sata SATA Host
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4 pex0 PCIe Cntrl 0
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5 pex1 PCIe Cntrl 1
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8 sdio0 SDHCI Host 0
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9 sdio1 SDHCI Host 1
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10 nand NAND Cntrl
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11 camera Camera Cntrl
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12 i2s0 I2S Cntrl 0
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13 i2s1 I2S Cntrl 1
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15 crypto CESA engine
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21 ac97 AC97 Cntrl
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22 pdma Peripheral DMA
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23 xor0 XOR DMA 0
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24 xor1 XOR DMA 1
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30 gephy Gigabit Ethernel PHY
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Note: gephy(30) is implemented as a parent clock of ge(2)
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The following is a list of provided IDs for Kirkwood:
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ID Clock Peripheral
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-----------------------------------
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0 ge0 Gigabit Ethernet 0
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2 pex0 PCIe Cntrl 0
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3 usb0 USB Host 0
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4 sdio SDIO Cntrl
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5 tsu Transp. Stream Unit
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6 dunit SDRAM Cntrl
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7 runit Runit
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8 xor0 XOR DMA 0
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9 audio I2S Cntrl 0
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14 sata0 SATA Host 0
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15 sata1 SATA Host 1
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16 xor1 XOR DMA 1
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17 crypto CESA engine
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18 pex1 PCIe Cntrl 1
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19 ge1 Gigabit Ethernet 1
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20 tdm Time Division Mplx
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Required properties:
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- compatible : shall be one of the following:
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"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
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"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
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"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
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"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
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"marvell,dove-gating-clock" - for Dove SoC clock gating
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"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
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- reg : shall be the register address of the Clock Gating Control register
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- #clock-cells : from common clock binding; shall be set to 1
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Optional properties:
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- clocks : default parent clock phandle (e.g. tclk)
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Example:
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gate_clk: clock-gating-control@d0038 {
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compatible = "marvell,dove-gating-clock";
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reg = <0xd0038 0x4>;
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/* default parent clock is tclk */
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clocks = <&core_clk 0>;
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#clock-cells = <1>;
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};
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sdio0: sdio@92000 {
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compatible = "marvell,dove-sdhci";
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/* get clk gate bit 8 (sdio0) */
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clocks = <&gate_clk 8>;
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};
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