576 lines
15 KiB
C
576 lines
15 KiB
C
/*
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* Copyright 2009 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_i2c.h"
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#include "nouveau_encoder.h"
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static int
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auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_i2c_chan *auxch;
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int ret;
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auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
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if (!auxch)
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return -ENODEV;
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ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
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if (ret)
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return ret;
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return 0;
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}
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static int
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auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_i2c_chan *auxch;
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int ret;
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auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
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if (!auxch)
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return -ENODEV;
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ret = nouveau_dp_auxch(auxch, 8, address, buf, size);
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return ret;
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}
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static int
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nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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uint32_t tmp;
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int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
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tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
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tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED |
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NV50_SOR_DP_CTRL_LANE_MASK);
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tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16;
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if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN)
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tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED;
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nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
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return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1);
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}
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static int
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nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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uint32_t tmp;
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int reg = 0x614300 + (nv_encoder->or * 0x800);
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tmp = nv_rd32(dev, reg);
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tmp &= 0xfff3ffff;
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if (cmd == DP_LINK_BW_2_7)
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tmp |= 0x00040000;
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nv_wr32(dev, reg, tmp);
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return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1);
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}
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static int
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nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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uint32_t tmp;
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uint8_t cmd;
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int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
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int ret;
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tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
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tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN;
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tmp |= (pattern << 24);
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nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
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ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
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if (ret)
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return ret;
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cmd &= ~DP_TRAINING_PATTERN_MASK;
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cmd |= (pattern & DP_TRAINING_PATTERN_MASK);
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return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
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}
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static int
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nouveau_dp_max_voltage_swing(struct drm_encoder *encoder)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct bit_displayport_encoder_table_entry *dpse;
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struct bit_displayport_encoder_table *dpe;
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int i, dpe_headerlen, max_vs = 0;
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dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
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if (!dpe)
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return false;
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dpse = (void *)((char *)dpe + dpe_headerlen);
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for (i = 0; i < dpe_headerlen; i++, dpse++) {
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if (dpse->vs_level > max_vs)
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max_vs = dpse->vs_level;
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}
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return max_vs;
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}
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static int
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nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct bit_displayport_encoder_table_entry *dpse;
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struct bit_displayport_encoder_table *dpe;
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int i, dpe_headerlen, max_pre = 0;
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dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
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if (!dpe)
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return false;
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dpse = (void *)((char *)dpe + dpe_headerlen);
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for (i = 0; i < dpe_headerlen; i++, dpse++) {
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if (dpse->vs_level != vs)
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continue;
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if (dpse->pre_level > max_pre)
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max_pre = dpse->pre_level;
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}
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return max_pre;
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}
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static bool
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nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct bit_displayport_encoder_table_entry *dpse;
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struct bit_displayport_encoder_table *dpe;
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int ret, i, dpe_headerlen, vs = 0, pre = 0;
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uint8_t request[2];
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dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
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if (!dpe)
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return false;
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dpse = (void *)((char *)dpe + dpe_headerlen);
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ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2);
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if (ret)
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return false;
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NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
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/* Keep all lanes at the same level.. */
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for (i = 0; i < nv_encoder->dp.link_nr; i++) {
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int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf;
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int lane_vs = lane_req & 3;
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int lane_pre = (lane_req >> 2) & 3;
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if (lane_vs > vs)
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vs = lane_vs;
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if (lane_pre > pre)
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pre = lane_pre;
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}
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if (vs >= nouveau_dp_max_voltage_swing(encoder)) {
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vs = nouveau_dp_max_voltage_swing(encoder);
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vs |= 4;
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}
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if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) {
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pre = nouveau_dp_max_pre_emphasis(encoder, vs & 3);
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pre |= 4;
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}
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/* Update the configuration for all lanes.. */
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for (i = 0; i < nv_encoder->dp.link_nr; i++)
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config[i] = (pre << 3) | vs;
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return true;
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}
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static bool
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nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct bit_displayport_encoder_table_entry *dpse;
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struct bit_displayport_encoder_table *dpe;
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int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
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int dpe_headerlen, ret, i;
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NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
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config[0], config[1], config[2], config[3]);
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dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
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if (!dpe)
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return false;
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dpse = (void *)((char *)dpe + dpe_headerlen);
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for (i = 0; i < dpe->record_nr; i++, dpse++) {
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if (dpse->vs_level == (config[0] & 3) &&
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dpse->pre_level == ((config[0] >> 3) & 3))
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break;
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}
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BUG_ON(i == dpe->record_nr);
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for (i = 0; i < nv_encoder->dp.link_nr; i++) {
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const int shift[4] = { 16, 8, 0, 24 };
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uint32_t mask = 0xff << shift[i];
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uint32_t reg0, reg1, reg2;
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reg0 = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask;
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reg0 |= (dpse->reg0 << shift[i]);
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reg1 = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask;
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reg1 |= (dpse->reg1 << shift[i]);
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reg2 = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff;
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reg2 |= (dpse->reg2 << 8);
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nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0);
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nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1);
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nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2);
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}
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ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4);
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if (ret)
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return false;
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return true;
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}
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bool
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nouveau_dp_link_train(struct drm_encoder *encoder)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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uint8_t config[4];
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uint8_t status[3];
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bool cr_done, cr_max_vs, eq_done;
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int ret = 0, i, tries, voltage;
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NV_DEBUG_KMS(dev, "link training!!\n");
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train:
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cr_done = eq_done = false;
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/* set link configuration */
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NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
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nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
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ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
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if (ret)
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return false;
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config[0] = nv_encoder->dp.link_nr;
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if (nv_encoder->dp.dpcd_version >= 0x11)
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config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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ret = nouveau_dp_lane_count_set(encoder, config[0]);
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if (ret)
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return false;
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/* clock recovery */
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NV_DEBUG_KMS(dev, "\tbegin cr\n");
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ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
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if (ret)
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goto stop;
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tries = 0;
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voltage = -1;
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memset(config, 0x00, sizeof(config));
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for (;;) {
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if (!nouveau_dp_link_train_commit(encoder, config))
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break;
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udelay(100);
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ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
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if (ret)
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break;
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NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
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status[0], status[1]);
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cr_done = true;
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cr_max_vs = false;
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for (i = 0; i < nv_encoder->dp.link_nr; i++) {
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int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
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if (!(lane & DP_LANE_CR_DONE)) {
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cr_done = false;
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if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED)
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cr_max_vs = true;
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break;
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}
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}
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if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
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voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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tries = 0;
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}
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if (cr_done || cr_max_vs || (++tries == 5))
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break;
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if (!nouveau_dp_link_train_adjust(encoder, config))
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break;
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}
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if (!cr_done)
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goto stop;
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/* channel equalisation */
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NV_DEBUG_KMS(dev, "\tbegin eq\n");
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ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
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if (ret)
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goto stop;
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for (tries = 0; tries <= 5; tries++) {
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udelay(400);
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ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
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if (ret)
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break;
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NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
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status[0], status[1]);
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eq_done = true;
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if (!(status[2] & DP_INTERLANE_ALIGN_DONE))
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eq_done = false;
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for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) {
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int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
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if (!(lane & DP_LANE_CR_DONE)) {
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cr_done = false;
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break;
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}
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if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
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!(lane & DP_LANE_SYMBOL_LOCKED)) {
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eq_done = false;
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break;
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}
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}
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if (eq_done || !cr_done)
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break;
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if (!nouveau_dp_link_train_adjust(encoder, config) ||
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!nouveau_dp_link_train_commit(encoder, config))
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break;
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}
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stop:
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/* end link training */
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ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE);
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if (ret)
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return false;
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/* retry at a lower setting, if possible */
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if (!ret && !(eq_done && cr_done)) {
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NV_DEBUG_KMS(dev, "\twe failed\n");
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if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
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NV_DEBUG_KMS(dev, "retry link training at low rate\n");
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nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
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goto train;
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}
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}
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return eq_done;
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}
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bool
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nouveau_dp_detect(struct drm_encoder *encoder)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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uint8_t dpcd[4];
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int ret;
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ret = auxch_rd(encoder, 0x0000, dpcd, 4);
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if (ret)
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return false;
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NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
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"display: link_bw %d, link_nr %d version 0x%02x\n",
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nv_encoder->dcb->dpconf.link_bw,
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nv_encoder->dcb->dpconf.link_nr,
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dpcd[1], dpcd[2] & 0x0f, dpcd[0]);
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nv_encoder->dp.dpcd_version = dpcd[0];
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nv_encoder->dp.link_bw = dpcd[1];
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if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 &&
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!nv_encoder->dcb->dpconf.link_bw)
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nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
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nv_encoder->dp.link_nr = dpcd[2] & 0xf;
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if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr)
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nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
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return true;
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}
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int
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nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
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uint8_t *data, int data_nr)
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{
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struct drm_device *dev = auxch->dev;
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uint32_t tmp, ctrl, stat = 0, data32[4] = {};
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int ret = 0, i, index = auxch->rd;
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NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
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tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
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nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
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tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
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if (!(tmp & 0x01000000)) {
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NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp);
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ret = -EIO;
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goto out;
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}
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for (i = 0; i < 3; i++) {
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tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd));
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if (tmp & NV50_AUXCH_STAT_STATE_READY)
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break;
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udelay(100);
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}
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if (i == 3) {
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ret = -EBUSY;
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goto out;
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}
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if (!(cmd & 1)) {
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memcpy(data32, data, data_nr);
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for (i = 0; i < 4; i++) {
|
|
NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
|
|
nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
|
|
}
|
|
}
|
|
|
|
nv_wr32(dev, NV50_AUXCH_ADDR(index), addr);
|
|
ctrl = nv_rd32(dev, NV50_AUXCH_CTRL(index));
|
|
ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN);
|
|
ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
|
|
ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
|
|
|
|
for (;;) {
|
|
nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
|
|
nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
|
|
nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
|
|
if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) {
|
|
NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
|
|
nv_rd32(dev, NV50_AUXCH_CTRL(index)));
|
|
ret = -EBUSY;
|
|
goto out;
|
|
}
|
|
|
|
udelay(400);
|
|
|
|
stat = nv_rd32(dev, NV50_AUXCH_STAT(index));
|
|
if ((stat & NV50_AUXCH_STAT_REPLY_AUX) !=
|
|
NV50_AUXCH_STAT_REPLY_AUX_DEFER)
|
|
break;
|
|
}
|
|
|
|
if (cmd & 1) {
|
|
if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
|
|
ret = -EREMOTEIO;
|
|
goto out;
|
|
}
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
|
|
NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
|
|
}
|
|
memcpy(data, data32, data_nr);
|
|
}
|
|
|
|
out:
|
|
tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
|
|
nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000);
|
|
tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
|
|
if (tmp & 0x01000000) {
|
|
NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp);
|
|
ret = -EIO;
|
|
}
|
|
|
|
udelay(400);
|
|
|
|
return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY);
|
|
}
|
|
|
|
int
|
|
nouveau_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
|
|
uint8_t write_byte, uint8_t *read_byte)
|
|
{
|
|
struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
|
|
struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adapter;
|
|
struct drm_device *dev = auxch->dev;
|
|
int ret = 0, cmd, addr = algo_data->address;
|
|
uint8_t *buf;
|
|
|
|
if (mode == MODE_I2C_READ) {
|
|
cmd = AUX_I2C_READ;
|
|
buf = read_byte;
|
|
} else {
|
|
cmd = (mode & MODE_I2C_READ) ? AUX_I2C_READ : AUX_I2C_WRITE;
|
|
buf = &write_byte;
|
|
}
|
|
|
|
if (!(mode & MODE_I2C_STOP))
|
|
cmd |= AUX_I2C_MOT;
|
|
|
|
if (mode & MODE_I2C_START)
|
|
return 1;
|
|
|
|
for (;;) {
|
|
ret = nouveau_dp_auxch(auxch, cmd, addr, buf, 1);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
switch (ret & NV50_AUXCH_STAT_REPLY_I2C) {
|
|
case NV50_AUXCH_STAT_REPLY_I2C_ACK:
|
|
return 1;
|
|
case NV50_AUXCH_STAT_REPLY_I2C_NACK:
|
|
return -EREMOTEIO;
|
|
case NV50_AUXCH_STAT_REPLY_I2C_DEFER:
|
|
udelay(100);
|
|
break;
|
|
default:
|
|
NV_ERROR(dev, "invalid auxch status: 0x%08x\n", ret);
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
}
|
|
|