155 lines
3.9 KiB
C
155 lines
3.9 KiB
C
/*
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* Copyright 2014 Google, Inc
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* Author: Alexandru M Stan <amstan@chromium.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include "clk.h"
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struct rockchip_mmc_clock {
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struct clk_hw hw;
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void __iomem *reg;
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int id;
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int shift;
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};
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#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
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#define RK3288_MMC_CLKGEN_DIV 2
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static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return parent_rate / RK3288_MMC_CLKGEN_DIV;
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}
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#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
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#define ROCKCHIP_MMC_DEGREE_MASK 0x3
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#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
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#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
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#define PSECS_PER_SEC 1000000000000LL
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/*
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* Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to
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* simplify calculations. So 45degs could be anywhere between 33deg and 66deg.
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*/
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#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
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static int rockchip_mmc_get_phase(struct clk_hw *hw)
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{
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struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
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unsigned long rate = clk_get_rate(hw->clk);
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u32 raw_value;
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u16 degrees;
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u32 delay_num = 0;
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raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
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degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
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if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
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/* degrees/delaynum * 10000 */
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unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
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36 * (rate / 1000000);
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delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
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delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
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degrees += delay_num * factor / 10000;
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}
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return degrees % 360;
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}
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static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
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{
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struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
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unsigned long rate = clk_get_rate(hw->clk);
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u8 nineties, remainder;
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u8 delay_num;
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u32 raw_value;
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u64 delay;
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/* allow 22 to be 22.5 */
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degrees++;
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/* floor to 22.5 increment */
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degrees -= ((degrees) * 10 % 225) / 10;
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nineties = degrees / 90;
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/* 22.5 multiples */
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remainder = (degrees % 90) / 22;
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delay = PSECS_PER_SEC;
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do_div(delay, rate);
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/* / 360 / 22.5 */
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do_div(delay, 16);
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do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);
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delay *= remainder;
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delay_num = (u8) min(delay, 255ULL);
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raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
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raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
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raw_value |= nineties;
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writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg);
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pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
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__clk_get_name(hw->clk), degrees, delay_num,
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mmc_clock->reg, raw_value>>(mmc_clock->shift),
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rockchip_mmc_get_phase(hw)
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);
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return 0;
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}
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static const struct clk_ops rockchip_mmc_clk_ops = {
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.recalc_rate = rockchip_mmc_recalc,
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.get_phase = rockchip_mmc_get_phase,
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.set_phase = rockchip_mmc_set_phase,
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};
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struct clk *rockchip_clk_register_mmc(const char *name,
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const char *const *parent_names, u8 num_parents,
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void __iomem *reg, int shift)
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{
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struct clk_init_data init;
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struct rockchip_mmc_clock *mmc_clock;
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struct clk *clk;
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mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
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if (!mmc_clock)
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return NULL;
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init.num_parents = num_parents;
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init.parent_names = parent_names;
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init.ops = &rockchip_mmc_clk_ops;
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mmc_clock->hw.init = &init;
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mmc_clock->reg = reg;
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mmc_clock->shift = shift;
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if (name)
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init.name = name;
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clk = clk_register(NULL, &mmc_clock->hw);
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if (IS_ERR(clk))
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goto err_free;
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return clk;
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err_free:
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kfree(mmc_clock);
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return NULL;
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}
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