162 lines
4.0 KiB
C
162 lines
4.0 KiB
C
/*
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* Based on arch/arm/include/asm/mmu_context.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_MMU_CONTEXT_H
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#define __ASM_MMU_CONTEXT_H
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <asm/cacheflush.h>
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#include <asm/proc-fns.h>
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#include <asm-generic/mm_hooks.h>
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#include <asm/cputype.h>
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#include <asm/pgtable.h>
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#define MAX_ASID_BITS 16
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extern unsigned int cpu_last_asid;
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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void __new_context(struct mm_struct *mm);
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#ifdef CONFIG_PID_IN_CONTEXTIDR
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static inline void contextidr_thread_switch(struct task_struct *next)
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{
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asm(
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" msr contextidr_el1, %0\n"
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" isb"
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:
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: "r" (task_pid_nr(next)));
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}
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#else
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static inline void contextidr_thread_switch(struct task_struct *next)
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{
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}
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#endif
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/*
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* Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
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*/
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static inline void cpu_set_reserved_ttbr0(void)
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{
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unsigned long ttbr = page_to_phys(empty_zero_page);
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asm(
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" msr ttbr0_el1, %0 // set TTBR0\n"
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" isb"
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:
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: "r" (ttbr));
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}
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static inline void switch_new_context(struct mm_struct *mm)
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{
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unsigned long flags;
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__new_context(mm);
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local_irq_save(flags);
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cpu_switch_mm(mm->pgd, mm);
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local_irq_restore(flags);
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}
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static inline void check_and_switch_context(struct mm_struct *mm,
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struct task_struct *tsk)
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{
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/*
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* Required during context switch to avoid speculative page table
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* walking with the wrong TTBR.
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*/
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cpu_set_reserved_ttbr0();
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if (!((mm->context.id ^ cpu_last_asid) >> MAX_ASID_BITS))
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/*
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* The ASID is from the current generation, just switch to the
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* new pgd. This condition is only true for calls from
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* context_switch() and interrupts are already disabled.
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*/
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cpu_switch_mm(mm->pgd, mm);
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else if (irqs_disabled())
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/*
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* Defer the new ASID allocation until after the context
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* switch critical region since __new_context() cannot be
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* called with interrupts disabled.
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*/
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set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
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else
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/*
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* That is a direct call to switch_mm() or activate_mm() with
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* interrupts enabled and a new context.
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*/
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switch_new_context(mm);
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}
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#define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0)
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#define destroy_context(mm) do { } while(0)
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#define finish_arch_post_lock_switch \
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finish_arch_post_lock_switch
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static inline void finish_arch_post_lock_switch(void)
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{
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if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
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struct mm_struct *mm = current->mm;
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unsigned long flags;
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__new_context(mm);
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local_irq_save(flags);
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cpu_switch_mm(mm->pgd, mm);
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local_irq_restore(flags);
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}
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}
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/*
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* This is called when "tsk" is about to enter lazy TLB mode.
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*
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* mm: describes the currently active mm context
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* tsk: task which is entering lazy tlb
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* cpu: cpu number which is entering lazy tlb
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*
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* tsk->mm will be NULL
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*/
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static inline void
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enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/*
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* This is the actual mm switch as far as the scheduler
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* is concerned. No registers are touched. We avoid
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* calling the CPU specific function when the mm hasn't
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* actually changed.
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*/
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next)
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check_and_switch_context(next, tsk);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(prev,next) switch_mm(prev, next, NULL)
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#endif
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