Zhang Rui 15793a23ee powercap: intel_rapl: support new layout of Psys PowerLimit Register on SPR ... commit 931da6a0de upstream. On Sapphire Rapids, the layout of the Psys domain Power Limit Register is different from from what it was before. Enhance the code to support the new Psys PL register layout. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Reported-and-tested-by: Alkattan Dana <dana.alkattan@intel.com> [ rjw: Subject and changelog edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: Chen Zhuo <sagazchen@tencent.com> Signed-off-by: Xinghui Li <korantli@tencent.com>		2024-06-11 21:17:53 +08:00
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Kconfig	intel_rapl: abstract RAPL common code	2019-07-11 15:08:58 +02:00
Makefile	intel_rapl: abstract RAPL common code	2019-07-11 15:08:58 +02:00
idle_inject.c	powercap: idle_inject: Use higher resolution for idle injection	2019-09-03 11:33:29 +02:00
intel_rapl_common.c	powercap: intel_rapl: support new layout of Psys PowerLimit Register on SPR	2024-06-11 21:17:53 +08:00
intel_rapl_msr.c	intel_rapl: Fix module autoloading issue	2019-07-11 15:08:58 +02:00
powercap_sys.c	ock: sync codes to ock 5.4.119-20.0009.21	2024-06-11 20:27:38 +08:00