132 lines
3.8 KiB
C
132 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* cap_audit.h - audit iommu capabilities header
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*
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* Copyright (C) 2021 Intel Corporation
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*
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* Author: Kyung Min Park <kyung.min.park@intel.com>
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*/
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/*
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* Capability Register Mask
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*/
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#define CAP_FL5LP_MASK BIT_ULL(60)
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#define CAP_PI_MASK BIT_ULL(59)
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#define CAP_FL1GP_MASK BIT_ULL(56)
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#define CAP_RD_MASK BIT_ULL(55)
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#define CAP_WD_MASK BIT_ULL(54)
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#define CAP_MAMV_MASK GENMASK_ULL(53, 48)
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#define CAP_NFR_MASK GENMASK_ULL(47, 40)
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#define CAP_PSI_MASK BIT_ULL(39)
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#define CAP_SLLPS_MASK GENMASK_ULL(37, 34)
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#define CAP_FRO_MASK GENMASK_ULL(33, 24)
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#define CAP_ZLR_MASK BIT_ULL(22)
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#define CAP_MGAW_MASK GENMASK_ULL(21, 16)
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#define CAP_SAGAW_MASK GENMASK_ULL(12, 8)
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#define CAP_CM_MASK BIT_ULL(7)
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#define CAP_PHMR_MASK BIT_ULL(6)
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#define CAP_PLMR_MASK BIT_ULL(5)
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#define CAP_RWBF_MASK BIT_ULL(4)
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#define CAP_AFL_MASK BIT_ULL(3)
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#define CAP_NDOMS_MASK GENMASK_ULL(2, 0)
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/*
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* Extended Capability Register Mask
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*/
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#define ECAP_RPS_MASK BIT_ULL(49)
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#define ECAP_SMPWC_MASK BIT_ULL(48)
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#define ECAP_FLTS_MASK BIT_ULL(47)
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#define ECAP_SLTS_MASK BIT_ULL(46)
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#define ECAP_SLADS_MASK BIT_ULL(45)
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#define ECAP_VCS_MASK BIT_ULL(44)
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#define ECAP_SMTS_MASK BIT_ULL(43)
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#define ECAP_PDS_MASK BIT_ULL(42)
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#define ECAP_DIT_MASK BIT_ULL(41)
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#define ECAP_PASID_MASK BIT_ULL(40)
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#define ECAP_PSS_MASK GENMASK_ULL(39, 35)
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#define ECAP_EAFS_MASK BIT_ULL(34)
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#define ECAP_NWFS_MASK BIT_ULL(33)
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#define ECAP_SRS_MASK BIT_ULL(31)
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#define ECAP_ERS_MASK BIT_ULL(30)
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#define ECAP_PRS_MASK BIT_ULL(29)
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#define ECAP_NEST_MASK BIT_ULL(26)
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#define ECAP_MTS_MASK BIT_ULL(25)
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#define ECAP_MHMV_MASK GENMASK_ULL(23, 20)
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#define ECAP_IRO_MASK GENMASK_ULL(17, 8)
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#define ECAP_SC_MASK BIT_ULL(7)
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#define ECAP_PT_MASK BIT_ULL(6)
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#define ECAP_EIM_MASK BIT_ULL(4)
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#define ECAP_DT_MASK BIT_ULL(2)
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#define ECAP_QI_MASK BIT_ULL(1)
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#define ECAP_C_MASK BIT_ULL(0)
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/*
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* u64 intel_iommu_cap_sanity, intel_iommu_ecap_sanity will be adjusted as each
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* IOMMU gets audited.
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*/
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#define DO_CHECK_FEATURE_MISMATCH(a, b, cap, feature, MASK) \
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do { \
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if (cap##_##feature(a) != cap##_##feature(b)) { \
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intel_iommu_##cap##_sanity &= ~(MASK); \
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pr_info("IOMMU feature %s inconsistent", #feature); \
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} \
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} while (0)
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#define CHECK_FEATURE_MISMATCH(a, b, cap, feature, MASK) \
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DO_CHECK_FEATURE_MISMATCH((a)->cap, (b)->cap, cap, feature, MASK)
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#define CHECK_FEATURE_MISMATCH_HOTPLUG(b, cap, feature, MASK) \
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do { \
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if (cap##_##feature(intel_iommu_##cap##_sanity)) \
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DO_CHECK_FEATURE_MISMATCH(intel_iommu_##cap##_sanity, \
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(b)->cap, cap, feature, MASK); \
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} while (0)
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#define MINIMAL_FEATURE_IOMMU(iommu, cap, MASK) \
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do { \
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u64 min_feature = intel_iommu_##cap##_sanity & (MASK); \
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min_feature = min_t(u64, min_feature, (iommu)->cap & (MASK)); \
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intel_iommu_##cap##_sanity = (intel_iommu_##cap##_sanity & ~(MASK)) | \
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min_feature; \
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} while (0)
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#define MINIMAL_FEATURE_HOTPLUG(iommu, cap, feature, MASK, mismatch) \
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do { \
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if ((intel_iommu_##cap##_sanity & (MASK)) > \
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(cap##_##feature((iommu)->cap))) \
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mismatch = true; \
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else \
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(iommu)->cap = ((iommu)->cap & ~(MASK)) | \
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(intel_iommu_##cap##_sanity & (MASK)); \
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} while (0)
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enum cap_audit_type {
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CAP_AUDIT_STATIC_DMAR,
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CAP_AUDIT_STATIC_IRQR,
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CAP_AUDIT_HOTPLUG_DMAR,
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CAP_AUDIT_HOTPLUG_IRQR,
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};
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bool intel_cap_smts_sanity(void);
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bool intel_cap_pasid_sanity(void);
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bool intel_cap_nest_sanity(void);
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bool intel_cap_flts_sanity(void);
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bool intel_cap_slts_sanity(void);
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static inline bool scalable_mode_support(void)
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{
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return (intel_iommu_sm && intel_cap_smts_sanity());
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}
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static inline bool pasid_mode_support(void)
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{
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return scalable_mode_support() && intel_cap_pasid_sanity();
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}
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static inline bool nested_mode_support(void)
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{
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return scalable_mode_support() && intel_cap_nest_sanity();
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}
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int intel_cap_audit(enum cap_audit_type type, struct intel_iommu *iommu);
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