615 lines
16 KiB
C
615 lines
16 KiB
C
/*
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* Renesas INTC External IRQ Pin Driver
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*
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/clk.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_data/irq-renesas-intc-irqpin.h>
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#include <linux/pm_runtime.h>
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#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
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#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
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#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
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#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
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#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
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#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
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#define INTC_IRQPIN_REG_NR_MANDATORY 5
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#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
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#define INTC_IRQPIN_REG_NR 6
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/* INTC external IRQ PIN hardware register access:
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*
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* SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
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* PRIO is read-write 32-bit with 4-bits per IRQ (**)
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* SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
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* MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
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* CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
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*
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* (*) May be accessed by more than one driver instance - lock needed
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* (**) Read-modify-write access by one driver instance - lock needed
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* (***) Accessed by one driver instance only - no locking needed
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*/
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struct intc_irqpin_iomem {
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void __iomem *iomem;
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unsigned long (*read)(void __iomem *iomem);
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void (*write)(void __iomem *iomem, unsigned long data);
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int width;
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};
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struct intc_irqpin_irq {
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int hw_irq;
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int requested_irq;
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int domain_irq;
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struct intc_irqpin_priv *p;
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};
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struct intc_irqpin_priv {
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struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
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struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
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struct renesas_intc_irqpin_config config;
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unsigned int number_of_irqs;
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struct platform_device *pdev;
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struct irq_chip irq_chip;
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struct irq_domain *irq_domain;
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struct clk *clk;
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bool shared_irqs;
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u8 shared_irq_mask;
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};
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struct intc_irqpin_irlm_config {
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unsigned int irlm_bit;
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};
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static unsigned long intc_irqpin_read32(void __iomem *iomem)
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{
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return ioread32(iomem);
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}
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static unsigned long intc_irqpin_read8(void __iomem *iomem)
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{
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return ioread8(iomem);
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}
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static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
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{
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iowrite32(data, iomem);
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}
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static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
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{
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iowrite8(data, iomem);
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}
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static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
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int reg)
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{
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struct intc_irqpin_iomem *i = &p->iomem[reg];
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return i->read(i->iomem);
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}
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static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
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int reg, unsigned long data)
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{
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struct intc_irqpin_iomem *i = &p->iomem[reg];
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i->write(i->iomem, data);
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}
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static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
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int reg, int hw_irq)
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{
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return BIT((p->iomem[reg].width - 1) - hw_irq);
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}
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static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
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int reg, int hw_irq)
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{
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intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
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}
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static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
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static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
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int reg, int shift,
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int width, int value)
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{
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unsigned long flags;
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unsigned long tmp;
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raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
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tmp = intc_irqpin_read(p, reg);
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tmp &= ~(((1 << width) - 1) << shift);
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tmp |= value << shift;
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intc_irqpin_write(p, reg, tmp);
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raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
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}
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static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
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int irq, int do_mask)
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{
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/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
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int bitfield_width = 4;
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int shift = 32 - (irq + 1) * bitfield_width;
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intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
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shift, bitfield_width,
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do_mask ? 0 : (1 << bitfield_width) - 1);
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}
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static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
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{
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/* The SENSE register is assumed to be 32-bit. */
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int bitfield_width = p->config.sense_bitfield_width;
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int shift = 32 - (irq + 1) * bitfield_width;
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dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
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if (value >= (1 << bitfield_width))
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return -EINVAL;
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intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
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bitfield_width, value);
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return 0;
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}
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static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
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{
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dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
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str, i->requested_irq, i->hw_irq, i->domain_irq);
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}
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static void intc_irqpin_irq_enable(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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intc_irqpin_dbg(&p->irq[hw_irq], "enable");
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intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
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}
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static void intc_irqpin_irq_disable(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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intc_irqpin_dbg(&p->irq[hw_irq], "disable");
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intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
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}
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static void intc_irqpin_shared_irq_enable(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
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intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
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p->shared_irq_mask &= ~BIT(hw_irq);
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}
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static void intc_irqpin_shared_irq_disable(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
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intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
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p->shared_irq_mask |= BIT(hw_irq);
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}
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static void intc_irqpin_irq_enable_force(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
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intc_irqpin_irq_enable(d);
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/* enable interrupt through parent interrupt controller,
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* assumes non-shared interrupt with 1:1 mapping
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* needed for busted IRQs on some SoCs like sh73a0
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*/
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irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
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}
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static void intc_irqpin_irq_disable_force(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
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/* disable interrupt through parent interrupt controller,
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* assumes non-shared interrupt with 1:1 mapping
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* needed for busted IRQs on some SoCs like sh73a0
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*/
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irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
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intc_irqpin_irq_disable(d);
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}
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#define INTC_IRQ_SENSE_VALID 0x10
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#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
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static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
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[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
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[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
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[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
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[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
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[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
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};
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static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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if (!(value & INTC_IRQ_SENSE_VALID))
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return -EINVAL;
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return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
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value ^ INTC_IRQ_SENSE_VALID);
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}
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static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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if (!p->clk)
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return 0;
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if (on)
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clk_enable(p->clk);
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else
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clk_disable(p->clk);
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return 0;
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}
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static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
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{
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struct intc_irqpin_irq *i = dev_id;
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struct intc_irqpin_priv *p = i->p;
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unsigned long bit;
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intc_irqpin_dbg(i, "demux1");
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bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
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if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
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intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
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intc_irqpin_dbg(i, "demux2");
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generic_handle_irq(i->domain_irq);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
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{
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struct intc_irqpin_priv *p = dev_id;
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unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
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irqreturn_t status = IRQ_NONE;
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int k;
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for (k = 0; k < 8; k++) {
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if (reg_source & BIT(7 - k)) {
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if (BIT(k) & p->shared_irq_mask)
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continue;
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status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
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}
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}
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return status;
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}
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static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct intc_irqpin_priv *p = h->host_data;
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p->irq[hw].domain_irq = virq;
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p->irq[hw].hw_irq = hw;
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intc_irqpin_dbg(&p->irq[hw], "map");
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irq_set_chip_data(virq, h->host_data);
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irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
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set_irq_flags(virq, IRQF_VALID); /* kill me now */
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return 0;
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}
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static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
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.map = intc_irqpin_irq_domain_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static const struct intc_irqpin_irlm_config intc_irqpin_irlm_r8a7779 = {
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.irlm_bit = 23, /* ICR0.IRLM0 */
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};
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static const struct of_device_id intc_irqpin_dt_ids[] = {
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{ .compatible = "renesas,intc-irqpin", },
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{ .compatible = "renesas,intc-irqpin-r8a7779",
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.data = &intc_irqpin_irlm_r8a7779 },
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{},
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};
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MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
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static int intc_irqpin_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct renesas_intc_irqpin_config *pdata = dev->platform_data;
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const struct of_device_id *of_id;
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struct intc_irqpin_priv *p;
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struct intc_irqpin_iomem *i;
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struct resource *io[INTC_IRQPIN_REG_NR];
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struct resource *irq;
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struct irq_chip *irq_chip;
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void (*enable_fn)(struct irq_data *d);
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void (*disable_fn)(struct irq_data *d);
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const char *name = dev_name(dev);
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int ref_irq;
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int ret;
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int k;
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p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
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if (!p) {
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dev_err(dev, "failed to allocate driver data\n");
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return -ENOMEM;
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}
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/* deal with driver instance configuration */
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if (pdata) {
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memcpy(&p->config, pdata, sizeof(*pdata));
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} else {
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of_property_read_u32(dev->of_node, "sense-bitfield-width",
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&p->config.sense_bitfield_width);
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p->config.control_parent = of_property_read_bool(dev->of_node,
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"control-parent");
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}
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if (!p->config.sense_bitfield_width)
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p->config.sense_bitfield_width = 4; /* default to 4 bits */
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p->pdev = pdev;
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platform_set_drvdata(pdev, p);
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p->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(p->clk)) {
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dev_warn(dev, "unable to get clock\n");
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p->clk = NULL;
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}
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pm_runtime_enable(dev);
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pm_runtime_get_sync(dev);
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/* get hold of register banks */
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memset(io, 0, sizeof(io));
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for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
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io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
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if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
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dev_err(dev, "not enough IOMEM resources\n");
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ret = -EINVAL;
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goto err0;
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}
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}
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/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
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for (k = 0; k < INTC_IRQPIN_MAX; k++) {
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
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if (!irq)
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break;
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p->irq[k].p = p;
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p->irq[k].requested_irq = irq->start;
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}
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p->number_of_irqs = k;
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if (p->number_of_irqs < 1) {
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dev_err(dev, "not enough IRQ resources\n");
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ret = -EINVAL;
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goto err0;
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}
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/* ioremap IOMEM and setup read/write callbacks */
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for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
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i = &p->iomem[k];
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/* handle optional registers */
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if (!io[k])
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continue;
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switch (resource_size(io[k])) {
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case 1:
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i->width = 8;
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i->read = intc_irqpin_read8;
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i->write = intc_irqpin_write8;
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break;
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case 4:
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i->width = 32;
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i->read = intc_irqpin_read32;
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i->write = intc_irqpin_write32;
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break;
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default:
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dev_err(dev, "IOMEM size mismatch\n");
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ret = -EINVAL;
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goto err0;
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}
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i->iomem = devm_ioremap_nocache(dev, io[k]->start,
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resource_size(io[k]));
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if (!i->iomem) {
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dev_err(dev, "failed to remap IOMEM\n");
|
|
ret = -ENXIO;
|
|
goto err0;
|
|
}
|
|
}
|
|
|
|
/* configure "individual IRQ mode" where needed */
|
|
of_id = of_match_device(intc_irqpin_dt_ids, dev);
|
|
if (of_id && of_id->data) {
|
|
const struct intc_irqpin_irlm_config *irlm_config = of_id->data;
|
|
|
|
if (io[INTC_IRQPIN_REG_IRLM])
|
|
intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
|
|
irlm_config->irlm_bit,
|
|
1, 1);
|
|
else
|
|
dev_warn(dev, "unable to select IRLM mode\n");
|
|
}
|
|
|
|
/* mask all interrupts using priority */
|
|
for (k = 0; k < p->number_of_irqs; k++)
|
|
intc_irqpin_mask_unmask_prio(p, k, 1);
|
|
|
|
/* clear all pending interrupts */
|
|
intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
|
|
|
|
/* scan for shared interrupt lines */
|
|
ref_irq = p->irq[0].requested_irq;
|
|
p->shared_irqs = true;
|
|
for (k = 1; k < p->number_of_irqs; k++) {
|
|
if (ref_irq != p->irq[k].requested_irq) {
|
|
p->shared_irqs = false;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* use more severe masking method if requested */
|
|
if (p->config.control_parent) {
|
|
enable_fn = intc_irqpin_irq_enable_force;
|
|
disable_fn = intc_irqpin_irq_disable_force;
|
|
} else if (!p->shared_irqs) {
|
|
enable_fn = intc_irqpin_irq_enable;
|
|
disable_fn = intc_irqpin_irq_disable;
|
|
} else {
|
|
enable_fn = intc_irqpin_shared_irq_enable;
|
|
disable_fn = intc_irqpin_shared_irq_disable;
|
|
}
|
|
|
|
irq_chip = &p->irq_chip;
|
|
irq_chip->name = name;
|
|
irq_chip->irq_mask = disable_fn;
|
|
irq_chip->irq_unmask = enable_fn;
|
|
irq_chip->irq_set_type = intc_irqpin_irq_set_type;
|
|
irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
|
|
irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
|
|
|
|
p->irq_domain = irq_domain_add_simple(dev->of_node,
|
|
p->number_of_irqs,
|
|
p->config.irq_base,
|
|
&intc_irqpin_irq_domain_ops, p);
|
|
if (!p->irq_domain) {
|
|
ret = -ENXIO;
|
|
dev_err(dev, "cannot initialize irq domain\n");
|
|
goto err0;
|
|
}
|
|
|
|
if (p->shared_irqs) {
|
|
/* request one shared interrupt */
|
|
if (devm_request_irq(dev, p->irq[0].requested_irq,
|
|
intc_irqpin_shared_irq_handler,
|
|
IRQF_SHARED, name, p)) {
|
|
dev_err(dev, "failed to request low IRQ\n");
|
|
ret = -ENOENT;
|
|
goto err1;
|
|
}
|
|
} else {
|
|
/* request interrupts one by one */
|
|
for (k = 0; k < p->number_of_irqs; k++) {
|
|
if (devm_request_irq(dev, p->irq[k].requested_irq,
|
|
intc_irqpin_irq_handler, 0, name,
|
|
&p->irq[k])) {
|
|
dev_err(dev, "failed to request low IRQ\n");
|
|
ret = -ENOENT;
|
|
goto err1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* unmask all interrupts on prio level */
|
|
for (k = 0; k < p->number_of_irqs; k++)
|
|
intc_irqpin_mask_unmask_prio(p, k, 0);
|
|
|
|
dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
|
|
|
|
/* warn in case of mismatch if irq base is specified */
|
|
if (p->config.irq_base) {
|
|
if (p->config.irq_base != p->irq[0].domain_irq)
|
|
dev_warn(dev, "irq base mismatch (%d/%d)\n",
|
|
p->config.irq_base, p->irq[0].domain_irq);
|
|
}
|
|
|
|
return 0;
|
|
|
|
err1:
|
|
irq_domain_remove(p->irq_domain);
|
|
err0:
|
|
pm_runtime_put(dev);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int intc_irqpin_remove(struct platform_device *pdev)
|
|
{
|
|
struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
|
|
|
|
irq_domain_remove(p->irq_domain);
|
|
pm_runtime_put(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver intc_irqpin_device_driver = {
|
|
.probe = intc_irqpin_probe,
|
|
.remove = intc_irqpin_remove,
|
|
.driver = {
|
|
.name = "renesas_intc_irqpin",
|
|
.of_match_table = intc_irqpin_dt_ids,
|
|
}
|
|
};
|
|
|
|
static int __init intc_irqpin_init(void)
|
|
{
|
|
return platform_driver_register(&intc_irqpin_device_driver);
|
|
}
|
|
postcore_initcall(intc_irqpin_init);
|
|
|
|
static void __exit intc_irqpin_exit(void)
|
|
{
|
|
platform_driver_unregister(&intc_irqpin_device_driver);
|
|
}
|
|
module_exit(intc_irqpin_exit);
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
|
|
MODULE_LICENSE("GPL v2");
|