843 lines
21 KiB
C
843 lines
21 KiB
C
#ifndef __ASM_X86_PROCESSOR_H
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#define __ASM_X86_PROCESSOR_H
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#include <asm/processor-flags.h>
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/* migration helpers, for KVM - will be removed in 2.6.25: */
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#include <asm/vm86.h>
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#define Xgt_desc_struct desc_ptr
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/* Forward declaration, a strange C thing */
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struct task_struct;
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struct mm_struct;
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#include <asm/vm86.h>
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#include <asm/math_emu.h>
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#include <asm/segment.h>
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#include <asm/types.h>
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#include <asm/sigcontext.h>
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#include <asm/current.h>
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#include <asm/cpufeature.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/percpu.h>
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#include <asm/msr.h>
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#include <asm/desc_defs.h>
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#include <asm/nops.h>
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#include <linux/personality.h>
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#include <linux/cpumask.h>
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#include <linux/cache.h>
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#include <linux/threads.h>
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#include <linux/init.h>
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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static inline void *current_text_addr(void)
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{
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void *pc;
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asm volatile("mov $1f,%0\n1:":"=r" (pc));
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return pc;
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}
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#ifdef CONFIG_X86_VSMP
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#define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
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#define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
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#else
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#define ARCH_MIN_TASKALIGN 16
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#define ARCH_MIN_MMSTRUCT_ALIGN 0
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#endif
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/*
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* CPU type and hardware bug flags. Kept separately for each CPU.
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* Members of this structure are referenced in head.S, so think twice
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* before touching them. [mj]
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*/
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struct cpuinfo_x86 {
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__u8 x86; /* CPU family */
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__u8 x86_vendor; /* CPU vendor */
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__u8 x86_model;
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__u8 x86_mask;
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#ifdef CONFIG_X86_32
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char wp_works_ok; /* It doesn't on 386's */
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char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
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char hard_math;
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char rfu;
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char fdiv_bug;
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char f00f_bug;
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char coma_bug;
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char pad0;
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#else
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/* number of 4K pages in DTLB/ITLB combined(in pages)*/
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int x86_tlbsize;
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__u8 x86_virt_bits, x86_phys_bits;
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/* cpuid returned core id bits */
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__u8 x86_coreid_bits;
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/* Max extended CPUID function supported */
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__u32 extended_cpuid_level;
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#endif
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int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
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__u32 x86_capability[NCAPINTS];
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char x86_vendor_id[16];
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char x86_model_id[64];
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int x86_cache_size; /* in KB - valid for CPUS which support this
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call */
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int x86_cache_alignment; /* In bytes */
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int x86_power;
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unsigned long loops_per_jiffy;
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#ifdef CONFIG_SMP
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cpumask_t llc_shared_map; /* cpus sharing the last level cache */
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#endif
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u16 x86_max_cores; /* cpuid returned max cores value */
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u16 apicid;
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u16 x86_clflush_size;
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#ifdef CONFIG_SMP
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u16 booted_cores; /* number of cores as seen by OS */
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u16 phys_proc_id; /* Physical processor id. */
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u16 cpu_core_id; /* Core id */
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u16 cpu_index; /* index into per_cpu list */
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#endif
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} __attribute__((__aligned__(SMP_CACHE_BYTES)));
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#define X86_VENDOR_INTEL 0
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#define X86_VENDOR_CYRIX 1
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#define X86_VENDOR_AMD 2
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#define X86_VENDOR_UMC 3
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#define X86_VENDOR_NEXGEN 4
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_NUM 9
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#define X86_VENDOR_UNKNOWN 0xff
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/*
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* capabilities of CPUs
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*/
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extern struct cpuinfo_x86 boot_cpu_data;
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extern struct cpuinfo_x86 new_cpu_data;
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extern struct tss_struct doublefault_tss;
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extern __u32 cleared_cpu_caps[NCAPINTS];
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#ifdef CONFIG_SMP
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DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
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#define cpu_data(cpu) per_cpu(cpu_info, cpu)
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#define current_cpu_data cpu_data(smp_processor_id())
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#else
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#define cpu_data(cpu) boot_cpu_data
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#define current_cpu_data boot_cpu_data
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#endif
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void cpu_detect(struct cpuinfo_x86 *c);
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extern void identify_cpu(struct cpuinfo_x86 *);
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extern void identify_boot_cpu(void);
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extern void identify_secondary_cpu(struct cpuinfo_x86 *);
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extern void print_cpu_info(struct cpuinfo_x86 *);
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extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
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extern unsigned short num_cache_leaves;
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#if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
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extern void detect_ht(struct cpuinfo_x86 *c);
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#else
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static inline void detect_ht(struct cpuinfo_x86 *c) {}
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#endif
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static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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/* ecx is often an input as well as an output. */
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__asm__("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (*eax), "2" (*ecx));
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}
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static inline void load_cr3(pgd_t *pgdir)
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{
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write_cr3(__pa(pgdir));
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}
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#ifdef CONFIG_X86_32
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/* This is the TSS defined by the hardware. */
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struct x86_hw_tss {
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unsigned short back_link, __blh;
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unsigned long sp0;
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unsigned short ss0, __ss0h;
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unsigned long sp1;
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unsigned short ss1, __ss1h; /* ss1 caches MSR_IA32_SYSENTER_CS */
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unsigned long sp2;
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unsigned short ss2, __ss2h;
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unsigned long __cr3;
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unsigned long ip;
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unsigned long flags;
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unsigned long ax, cx, dx, bx;
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unsigned long sp, bp, si, di;
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unsigned short es, __esh;
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unsigned short cs, __csh;
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unsigned short ss, __ssh;
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unsigned short ds, __dsh;
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unsigned short fs, __fsh;
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unsigned short gs, __gsh;
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unsigned short ldt, __ldth;
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unsigned short trace, io_bitmap_base;
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} __attribute__((packed));
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#else
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struct x86_hw_tss {
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u32 reserved1;
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u64 sp0;
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u64 sp1;
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u64 sp2;
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u64 reserved2;
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u64 ist[7];
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u32 reserved3;
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u32 reserved4;
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u16 reserved5;
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u16 io_bitmap_base;
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} __attribute__((packed)) ____cacheline_aligned;
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#endif
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/*
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* Size of io_bitmap.
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*/
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
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struct tss_struct {
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struct x86_hw_tss x86_tss;
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/*
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* The extra 1 is there because the CPU will access an
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* additional byte beyond the end of the IO permission
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* bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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/*
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* Cache the current maximum and the last task that used the bitmap:
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*/
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unsigned long io_bitmap_max;
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struct thread_struct *io_bitmap_owner;
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/*
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* pads the TSS to be cacheline-aligned (size is 0x100)
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*/
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unsigned long __cacheline_filler[35];
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/*
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* .. and then another 0x100 bytes for emergency kernel stack
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*/
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unsigned long stack[64];
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} __attribute__((packed));
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DECLARE_PER_CPU(struct tss_struct, init_tss);
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/* Save the original ist values for checking stack pointers during debugging */
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struct orig_ist {
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unsigned long ist[7];
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};
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#define MXCSR_DEFAULT 0x1f80
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struct i387_fsave_struct {
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u32 cwd;
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u32 swd;
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u32 twd;
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u32 fip;
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u32 fcs;
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u32 foo;
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u32 fos;
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u32 st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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u32 status; /* software status information */
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};
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struct i387_fxsave_struct {
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u16 cwd;
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u16 swd;
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u16 twd;
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u16 fop;
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union {
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struct {
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u64 rip;
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u64 rdp;
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};
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struct {
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u32 fip;
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u32 fcs;
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u32 foo;
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u32 fos;
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};
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};
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u32 mxcsr;
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u32 mxcsr_mask;
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u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
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u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
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u32 padding[24];
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} __attribute__((aligned(16)));
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struct i387_soft_struct {
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u32 cwd;
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u32 swd;
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u32 twd;
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u32 fip;
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u32 fcs;
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u32 foo;
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u32 fos;
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u32 st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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u8 ftop, changed, lookahead, no_update, rm, alimit;
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struct info *info;
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u32 entry_eip;
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};
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union i387_union {
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struct i387_fsave_struct fsave;
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struct i387_fxsave_struct fxsave;
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struct i387_soft_struct soft;
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};
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#ifdef CONFIG_X86_32
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DECLARE_PER_CPU(u8, cpu_llc_id);
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#else
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DECLARE_PER_CPU(struct orig_ist, orig_ist);
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#endif
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extern void print_cpu_info(struct cpuinfo_x86 *);
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extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
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extern unsigned short num_cache_leaves;
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struct thread_struct {
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/* cached TLS descriptors. */
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struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
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unsigned long sp0;
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unsigned long sp;
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#ifdef CONFIG_X86_32
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unsigned long sysenter_cs;
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#else
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unsigned long usersp; /* Copy from PDA */
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unsigned short es, ds, fsindex, gsindex;
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#endif
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unsigned long ip;
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unsigned long fs;
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unsigned long gs;
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/* Hardware debugging registers */
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unsigned long debugreg0;
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unsigned long debugreg1;
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unsigned long debugreg2;
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unsigned long debugreg3;
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unsigned long debugreg6;
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unsigned long debugreg7;
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/* fault info */
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unsigned long cr2, trap_no, error_code;
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/* floating point info */
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union i387_union i387 __attribute__((aligned(16)));;
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#ifdef CONFIG_X86_32
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/* virtual 86 mode info */
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struct vm86_struct __user *vm86_info;
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unsigned long screen_bitmap;
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unsigned long v86flags, v86mask, saved_sp0;
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unsigned int saved_fs, saved_gs;
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#endif
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/* IO permissions */
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unsigned long *io_bitmap_ptr;
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unsigned long iopl;
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/* max allowed port in the bitmap, in bytes: */
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unsigned io_bitmap_max;
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/* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
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unsigned long debugctlmsr;
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/* Debug Store - if not 0 points to a DS Save Area configuration;
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* goes into MSR_IA32_DS_AREA */
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unsigned long ds_area_msr;
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};
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static inline unsigned long native_get_debugreg(int regno)
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{
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unsigned long val = 0; /* Damn you, gcc! */
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switch (regno) {
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case 0:
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asm("mov %%db0, %0" :"=r" (val)); break;
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case 1:
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asm("mov %%db1, %0" :"=r" (val)); break;
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case 2:
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asm("mov %%db2, %0" :"=r" (val)); break;
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case 3:
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asm("mov %%db3, %0" :"=r" (val)); break;
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case 6:
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asm("mov %%db6, %0" :"=r" (val)); break;
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case 7:
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asm("mov %%db7, %0" :"=r" (val)); break;
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default:
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BUG();
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}
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return val;
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}
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static inline void native_set_debugreg(int regno, unsigned long value)
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{
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switch (regno) {
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case 0:
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asm("mov %0,%%db0" : /* no output */ :"r" (value));
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break;
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case 1:
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asm("mov %0,%%db1" : /* no output */ :"r" (value));
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break;
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case 2:
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asm("mov %0,%%db2" : /* no output */ :"r" (value));
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break;
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case 3:
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asm("mov %0,%%db3" : /* no output */ :"r" (value));
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break;
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case 6:
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asm("mov %0,%%db6" : /* no output */ :"r" (value));
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break;
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case 7:
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asm("mov %0,%%db7" : /* no output */ :"r" (value));
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break;
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default:
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BUG();
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}
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}
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/*
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* Set IOPL bits in EFLAGS from given mask
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*/
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static inline void native_set_iopl_mask(unsigned mask)
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{
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#ifdef CONFIG_X86_32
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unsigned int reg;
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__asm__ __volatile__ ("pushfl;"
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"popl %0;"
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"andl %1, %0;"
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"orl %2, %0;"
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"pushl %0;"
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"popfl"
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: "=&r" (reg)
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: "i" (~X86_EFLAGS_IOPL), "r" (mask));
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#endif
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}
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static inline void native_load_sp0(struct tss_struct *tss,
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struct thread_struct *thread)
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{
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tss->x86_tss.sp0 = thread->sp0;
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#ifdef CONFIG_X86_32
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/* Only happens when SEP is enabled, no need to test "SEP"arately */
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if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
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tss->x86_tss.ss1 = thread->sysenter_cs;
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wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
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}
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#endif
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}
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static inline void native_swapgs(void)
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{
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#ifdef CONFIG_X86_64
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asm volatile("swapgs" ::: "memory");
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#endif
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define __cpuid native_cpuid
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#define paravirt_enabled() 0
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/*
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* These special macros can be used to get or set a debugging register
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*/
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#define get_debugreg(var, register) \
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(var) = native_get_debugreg(register)
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#define set_debugreg(value, register) \
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native_set_debugreg(register, value)
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static inline void load_sp0(struct tss_struct *tss,
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struct thread_struct *thread)
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{
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native_load_sp0(tss, thread);
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}
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#define set_iopl_mask native_set_iopl_mask
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#define SWAPGS swapgs
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#endif /* CONFIG_PARAVIRT */
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/*
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* Save the cr4 feature set we're using (ie
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* Pentium 4MB enable and PPro Global page
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* enable), so that any CPU's that boot up
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* after us can get the correct flags.
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*/
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extern unsigned long mmu_cr4_features;
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static inline void set_in_cr4(unsigned long mask)
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{
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unsigned cr4;
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mmu_cr4_features |= mask;
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cr4 = read_cr4();
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cr4 |= mask;
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write_cr4(cr4);
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}
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static inline void clear_in_cr4(unsigned long mask)
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{
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unsigned cr4;
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mmu_cr4_features &= ~mask;
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cr4 = read_cr4();
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cr4 &= ~mask;
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write_cr4(cr4);
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}
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struct microcode_header {
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unsigned int hdrver;
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unsigned int rev;
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unsigned int date;
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unsigned int sig;
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unsigned int cksum;
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unsigned int ldrver;
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unsigned int pf;
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unsigned int datasize;
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unsigned int totalsize;
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unsigned int reserved[3];
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};
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struct microcode {
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struct microcode_header hdr;
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unsigned int bits[0];
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};
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typedef struct microcode microcode_t;
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typedef struct microcode_header microcode_header_t;
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/* microcode format is extended from prescott processors */
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struct extended_signature {
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unsigned int sig;
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unsigned int pf;
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unsigned int cksum;
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};
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struct extended_sigtable {
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|
unsigned int count;
|
|
unsigned int cksum;
|
|
unsigned int reserved[3];
|
|
struct extended_signature sigs[0];
|
|
};
|
|
|
|
typedef struct {
|
|
unsigned long seg;
|
|
} mm_segment_t;
|
|
|
|
|
|
/*
|
|
* create a kernel thread without removing it from tasklists
|
|
*/
|
|
extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
|
|
|
|
/* Free all resources held by a thread. */
|
|
extern void release_thread(struct task_struct *);
|
|
|
|
/* Prepare to copy thread state - unlazy all lazy status */
|
|
extern void prepare_to_copy(struct task_struct *tsk);
|
|
|
|
unsigned long get_wchan(struct task_struct *p);
|
|
|
|
/*
|
|
* Generic CPUID function
|
|
* clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
|
|
* resulting in stale register contents being returned.
|
|
*/
|
|
static inline void cpuid(unsigned int op,
|
|
unsigned int *eax, unsigned int *ebx,
|
|
unsigned int *ecx, unsigned int *edx)
|
|
{
|
|
*eax = op;
|
|
*ecx = 0;
|
|
__cpuid(eax, ebx, ecx, edx);
|
|
}
|
|
|
|
/* Some CPUID calls want 'count' to be placed in ecx */
|
|
static inline void cpuid_count(unsigned int op, int count,
|
|
unsigned int *eax, unsigned int *ebx,
|
|
unsigned int *ecx, unsigned int *edx)
|
|
{
|
|
*eax = op;
|
|
*ecx = count;
|
|
__cpuid(eax, ebx, ecx, edx);
|
|
}
|
|
|
|
/*
|
|
* CPUID functions returning a single datum
|
|
*/
|
|
static inline unsigned int cpuid_eax(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
return eax;
|
|
}
|
|
static inline unsigned int cpuid_ebx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
return ebx;
|
|
}
|
|
static inline unsigned int cpuid_ecx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
return ecx;
|
|
}
|
|
static inline unsigned int cpuid_edx(unsigned int op)
|
|
{
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
cpuid(op, &eax, &ebx, &ecx, &edx);
|
|
return edx;
|
|
}
|
|
|
|
/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
|
|
static inline void rep_nop(void)
|
|
{
|
|
__asm__ __volatile__("rep;nop": : :"memory");
|
|
}
|
|
|
|
/* Stop speculative execution */
|
|
static inline void sync_core(void)
|
|
{
|
|
int tmp;
|
|
asm volatile("cpuid" : "=a" (tmp) : "0" (1)
|
|
: "ebx", "ecx", "edx", "memory");
|
|
}
|
|
|
|
#define cpu_relax() rep_nop()
|
|
|
|
static inline void __monitor(const void *eax, unsigned long ecx,
|
|
unsigned long edx)
|
|
{
|
|
/* "monitor %eax,%ecx,%edx;" */
|
|
asm volatile(
|
|
".byte 0x0f,0x01,0xc8;"
|
|
: :"a" (eax), "c" (ecx), "d"(edx));
|
|
}
|
|
|
|
static inline void __mwait(unsigned long eax, unsigned long ecx)
|
|
{
|
|
/* "mwait %eax,%ecx;" */
|
|
asm volatile(
|
|
".byte 0x0f,0x01,0xc9;"
|
|
: :"a" (eax), "c" (ecx));
|
|
}
|
|
|
|
static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
|
|
{
|
|
/* "mwait %eax,%ecx;" */
|
|
asm volatile(
|
|
"sti; .byte 0x0f,0x01,0xc9;"
|
|
: :"a" (eax), "c" (ecx));
|
|
}
|
|
|
|
extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
|
|
|
|
extern int force_mwait;
|
|
|
|
extern void select_idle_routine(const struct cpuinfo_x86 *c);
|
|
|
|
extern unsigned long boot_option_idle_override;
|
|
|
|
extern void enable_sep_cpu(void);
|
|
extern int sysenter_setup(void);
|
|
|
|
/* Defined in head.S */
|
|
extern struct desc_ptr early_gdt_descr;
|
|
|
|
extern void cpu_set_gdt(int);
|
|
extern void switch_to_new_gdt(void);
|
|
extern void cpu_init(void);
|
|
extern void init_gdt(int cpu);
|
|
|
|
/* from system description table in BIOS. Mostly for MCA use, but
|
|
* others may find it useful. */
|
|
extern unsigned int machine_id;
|
|
extern unsigned int machine_submodel_id;
|
|
extern unsigned int BIOS_revision;
|
|
|
|
/* Boot loader type from the setup header */
|
|
extern int bootloader_type;
|
|
|
|
extern char ignore_fpu_irq;
|
|
#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
|
|
|
|
#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
|
|
#define ARCH_HAS_PREFETCHW
|
|
#define ARCH_HAS_SPINLOCK_PREFETCH
|
|
|
|
#ifdef CONFIG_X86_32
|
|
#define BASE_PREFETCH ASM_NOP4
|
|
#define ARCH_HAS_PREFETCH
|
|
#else
|
|
#define BASE_PREFETCH "prefetcht0 (%1)"
|
|
#endif
|
|
|
|
/* Prefetch instructions for Pentium III and AMD Athlon */
|
|
/* It's not worth to care about 3dnow! prefetches for the K6
|
|
because they are microcoded there and very slow.
|
|
However we don't do prefetches for pre XP Athlons currently
|
|
That should be fixed. */
|
|
static inline void prefetch(const void *x)
|
|
{
|
|
alternative_input(BASE_PREFETCH,
|
|
"prefetchnta (%1)",
|
|
X86_FEATURE_XMM,
|
|
"r" (x));
|
|
}
|
|
|
|
/* 3dnow! prefetch to get an exclusive cache line. Useful for
|
|
spinlocks to avoid one state transition in the cache coherency protocol. */
|
|
static inline void prefetchw(const void *x)
|
|
{
|
|
alternative_input(BASE_PREFETCH,
|
|
"prefetchw (%1)",
|
|
X86_FEATURE_3DNOW,
|
|
"r" (x));
|
|
}
|
|
|
|
#define spin_lock_prefetch(x) prefetchw(x)
|
|
#ifdef CONFIG_X86_32
|
|
/*
|
|
* User space process size: 3GB (default).
|
|
*/
|
|
#define TASK_SIZE (PAGE_OFFSET)
|
|
#define STACK_TOP TASK_SIZE
|
|
#define STACK_TOP_MAX STACK_TOP
|
|
|
|
#define INIT_THREAD { \
|
|
.sp0 = sizeof(init_stack) + (long)&init_stack, \
|
|
.vm86_info = NULL, \
|
|
.sysenter_cs = __KERNEL_CS, \
|
|
.io_bitmap_ptr = NULL, \
|
|
.fs = __KERNEL_PERCPU, \
|
|
}
|
|
|
|
/*
|
|
* Note that the .io_bitmap member must be extra-big. This is because
|
|
* the CPU will access an additional byte beyond the end of the IO
|
|
* permission bitmap. The extra byte must be all 1 bits, and must
|
|
* be within the limit.
|
|
*/
|
|
#define INIT_TSS { \
|
|
.x86_tss = { \
|
|
.sp0 = sizeof(init_stack) + (long)&init_stack, \
|
|
.ss0 = __KERNEL_DS, \
|
|
.ss1 = __KERNEL_CS, \
|
|
.io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
|
|
}, \
|
|
.io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
|
|
}
|
|
|
|
#define start_thread(regs, new_eip, new_esp) do { \
|
|
__asm__("movl %0,%%gs": :"r" (0)); \
|
|
regs->fs = 0; \
|
|
set_fs(USER_DS); \
|
|
regs->ds = __USER_DS; \
|
|
regs->es = __USER_DS; \
|
|
regs->ss = __USER_DS; \
|
|
regs->cs = __USER_CS; \
|
|
regs->ip = new_eip; \
|
|
regs->sp = new_esp; \
|
|
} while (0)
|
|
|
|
|
|
extern unsigned long thread_saved_pc(struct task_struct *tsk);
|
|
|
|
#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
|
|
#define KSTK_TOP(info) \
|
|
({ \
|
|
unsigned long *__ptr = (unsigned long *)(info); \
|
|
(unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
|
|
})
|
|
|
|
/*
|
|
* The below -8 is to reserve 8 bytes on top of the ring0 stack.
|
|
* This is necessary to guarantee that the entire "struct pt_regs"
|
|
* is accessable even if the CPU haven't stored the SS/ESP registers
|
|
* on the stack (interrupt gate does not save these registers
|
|
* when switching to the same priv ring).
|
|
* Therefore beware: accessing the ss/esp fields of the
|
|
* "struct pt_regs" is possible, but they may contain the
|
|
* completely wrong values.
|
|
*/
|
|
#define task_pt_regs(task) \
|
|
({ \
|
|
struct pt_regs *__regs__; \
|
|
__regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
|
|
__regs__ - 1; \
|
|
})
|
|
|
|
#define KSTK_ESP(task) (task_pt_regs(task)->sp)
|
|
|
|
#else
|
|
/*
|
|
* User space process size. 47bits minus one guard page.
|
|
*/
|
|
#define TASK_SIZE64 (0x800000000000UL - 4096)
|
|
|
|
/* This decides where the kernel will search for a free chunk of vm
|
|
* space during mmap's.
|
|
*/
|
|
#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
|
|
0xc0000000 : 0xFFFFe000)
|
|
|
|
#define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
|
|
IA32_PAGE_OFFSET : TASK_SIZE64)
|
|
#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
|
|
IA32_PAGE_OFFSET : TASK_SIZE64)
|
|
|
|
#define STACK_TOP TASK_SIZE
|
|
#define STACK_TOP_MAX TASK_SIZE64
|
|
|
|
#define INIT_THREAD { \
|
|
.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
|
|
}
|
|
|
|
#define INIT_TSS { \
|
|
.x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
|
|
}
|
|
|
|
#define start_thread(regs, new_rip, new_rsp) do { \
|
|
asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
|
|
load_gs_index(0); \
|
|
(regs)->ip = (new_rip); \
|
|
(regs)->sp = (new_rsp); \
|
|
write_pda(oldrsp, (new_rsp)); \
|
|
(regs)->cs = __USER_CS; \
|
|
(regs)->ss = __USER_DS; \
|
|
(regs)->flags = 0x200; \
|
|
set_fs(USER_DS); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Return saved PC of a blocked thread.
|
|
* What is this good for? it will be always the scheduler or ret_from_fork.
|
|
*/
|
|
#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
|
|
|
|
#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
|
|
#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
|
|
#endif /* CONFIG_X86_64 */
|
|
|
|
/* This decides where the kernel will search for a free chunk of vm
|
|
* space during mmap's.
|
|
*/
|
|
#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
|
|
|
|
#define KSTK_EIP(task) (task_pt_regs(task)->ip)
|
|
|
|
#endif
|