45 lines
1.7 KiB
Plaintext
45 lines
1.7 KiB
Plaintext
* ARM L2 Cache Controller
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ARM cores often have a separate level 2 cache controller. There are various
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implementations of the L2 cache controller with compatible programming models.
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The ARM L2 cache representation in the device tree should be done as follows:
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Required properties:
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- compatible : should be one of:
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"arm,pl310-cache"
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"arm,l220-cache"
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"arm,l210-cache"
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- cache-unified : Specifies the cache is a unified cache.
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- cache-level : Should be set to 2 for a level 2 cache.
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- reg : Physical base address and size of cache controller's memory mapped
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registers.
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Optional properties:
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- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Minimum valid values are 1. Controllers
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without setup latency control should use a value of 0.
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- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
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read, write and setup latencies. Controllers without setup latency control
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should use 0. Controllers without separate read and write Tag RAM latency
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values should only use the first cell.
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- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
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- arm,filter-ranges : <start length> Starting address and length of window to
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filter. Addresses in the filter window are directed to the M1 port. Other
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addresses will go to the M0 port.
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- interrupts : 1 combined interrupt.
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Example:
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L2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0xfff12000 0x1000>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <2 2 2>;
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arm,filter-latency = <0x80000000 0x8000000>;
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cache-unified;
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cache-level = <2>;
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interrupts = <45>;
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};
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