62 lines
2.0 KiB
Plaintext
62 lines
2.0 KiB
Plaintext
Analog Device AXI-DMAC DMA controller
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Required properties:
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- compatible: Must be "adi,axi-dmac-1.00.a".
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- reg: Specification for the controllers memory mapped register map.
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- interrupts: Specification for the controllers interrupt.
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- clocks: Phandle and specifier to the controllers AXI interface clock
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- #dma-cells: Must be 1.
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Required sub-nodes:
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- adi,channels: This sub-node must contain a sub-node for each DMA channel. For
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the channel sub-nodes the following bindings apply. They must match the
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configuration options of the peripheral as it was instantiated.
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Required properties for adi,channels sub-node:
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- #size-cells: Must be 0
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- #address-cells: Must be 1
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Required channel sub-node properties:
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- reg: Which channel this node refers to.
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- adi,length-width: Width of the DMA transfer length register.
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- adi,source-bus-width,
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adi,destination-bus-width: Width of the source or destination bus in bits.
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- adi,source-bus-type,
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adi,destination-bus-type: Type of the source or destination bus. Must be one
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of the following:
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0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
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1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
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2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
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Optional channel properties:
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- adi,cyclic: Must be set if the channel supports hardware cyclic DMA
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transfers.
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- adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
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DMA clients connected to the AXI-DMAC DMA controller must use the format
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described in the dma.txt file using a one-cell specifier. The value of the
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specifier refers to the DMA channel index.
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Example:
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dma: dma@7c420000 {
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compatible = "adi,axi-dmac-1.00.a";
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reg = <0x7c420000 0x10000>;
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interrupts = <0 57 0>;
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clocks = <&clkc 16>;
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#dma-cells = <1>;
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adi,channels {
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#size-cells = <0>;
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#address-cells = <1>;
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dma-channel@0 {
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reg = <0>;
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adi,source-bus-width = <32>;
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adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
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adi,destination-bus-width = <64>;
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adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
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};
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};
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};
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