156 lines
4.1 KiB
C
156 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) ST-Ericsson AB 2010
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* Author: Daniel Martensson / Daniel.Martensson@stericsson.com
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*/
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#ifndef CAIF_SPI_H_
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#define CAIF_SPI_H_
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#include <net/caif/caif_device.h>
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#define SPI_CMD_WR 0x00
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#define SPI_CMD_RD 0x01
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#define SPI_CMD_EOT 0x02
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#define SPI_CMD_IND 0x04
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#define SPI_DMA_BUF_LEN 8192
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#define WL_SZ 2 /* 16 bits. */
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#define SPI_CMD_SZ 4 /* 32 bits. */
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#define SPI_IND_SZ 4 /* 32 bits. */
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#define SPI_XFER 0
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#define SPI_SS_ON 1
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#define SPI_SS_OFF 2
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#define SPI_TERMINATE 3
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/* Minimum time between different levels is 50 microseconds. */
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#define MIN_TRANSITION_TIME_USEC 50
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/* Defines for calculating duration of SPI transfers for a particular
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* number of bytes.
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*/
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#define SPI_MASTER_CLK_MHZ 13
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#define SPI_XFER_TIME_USEC(bytes, clk) (((bytes) * 8) / clk)
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/* Normally this should be aligned on the modem in order to benefit from full
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* duplex transfers. However a size of 8188 provokes errors when running with
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* the modem. These errors occur when packet sizes approaches 4 kB of data.
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*/
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#define CAIF_MAX_SPI_FRAME 4092
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/* Maximum number of uplink CAIF frames that can reside in the same SPI frame.
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* This number should correspond with the modem setting. The application side
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* CAIF accepts any number of embedded downlink CAIF frames.
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*/
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#define CAIF_MAX_SPI_PKTS 9
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/* Decides if SPI buffers should be prefilled with 0xFF pattern for easier
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* debugging. Both TX and RX buffers will be filled before the transfer.
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*/
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#define CFSPI_DBG_PREFILL 0
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/* Structure describing a SPI transfer. */
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struct cfspi_xfer {
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u16 tx_dma_len;
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u16 rx_dma_len;
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void *va_tx[2];
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dma_addr_t pa_tx[2];
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void *va_rx;
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dma_addr_t pa_rx;
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};
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/* Structure implemented by the SPI interface. */
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struct cfspi_ifc {
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void (*ss_cb) (bool assert, struct cfspi_ifc *ifc);
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void (*xfer_done_cb) (struct cfspi_ifc *ifc);
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void *priv;
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};
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/* Structure implemented by SPI clients. */
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struct cfspi_dev {
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int (*init_xfer) (struct cfspi_xfer *xfer, struct cfspi_dev *dev);
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void (*sig_xfer) (bool xfer, struct cfspi_dev *dev);
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struct cfspi_ifc *ifc;
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char *name;
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u32 clk_mhz;
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void *priv;
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};
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/* Enumeration describing the CAIF SPI state. */
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enum cfspi_state {
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CFSPI_STATE_WAITING = 0,
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CFSPI_STATE_AWAKE,
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CFSPI_STATE_FETCH_PKT,
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CFSPI_STATE_GET_NEXT,
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CFSPI_STATE_INIT_XFER,
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CFSPI_STATE_WAIT_ACTIVE,
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CFSPI_STATE_SIG_ACTIVE,
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CFSPI_STATE_WAIT_XFER_DONE,
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CFSPI_STATE_XFER_DONE,
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CFSPI_STATE_WAIT_INACTIVE,
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CFSPI_STATE_SIG_INACTIVE,
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CFSPI_STATE_DELIVER_PKT,
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CFSPI_STATE_MAX,
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};
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/* Structure implemented by SPI physical interfaces. */
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struct cfspi {
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struct caif_dev_common cfdev;
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struct net_device *ndev;
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struct platform_device *pdev;
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struct sk_buff_head qhead;
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struct sk_buff_head chead;
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u16 cmd;
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u16 tx_cpck_len;
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u16 tx_npck_len;
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u16 rx_cpck_len;
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u16 rx_npck_len;
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struct cfspi_ifc ifc;
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struct cfspi_xfer xfer;
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struct cfspi_dev *dev;
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unsigned long state;
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struct work_struct work;
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struct workqueue_struct *wq;
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struct list_head list;
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int flow_off_sent;
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u32 qd_low_mark;
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u32 qd_high_mark;
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struct completion comp;
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wait_queue_head_t wait;
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spinlock_t lock;
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bool flow_stop;
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bool slave;
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bool slave_talked;
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#ifdef CONFIG_DEBUG_FS
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enum cfspi_state dbg_state;
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u16 pcmd;
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u16 tx_ppck_len;
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u16 rx_ppck_len;
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struct dentry *dbgfs_dir;
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struct dentry *dbgfs_state;
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struct dentry *dbgfs_frame;
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#endif /* CONFIG_DEBUG_FS */
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};
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extern int spi_frm_align;
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extern int spi_up_head_align;
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extern int spi_up_tail_align;
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extern int spi_down_head_align;
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extern int spi_down_tail_align;
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extern struct platform_driver cfspi_spi_driver;
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void cfspi_dbg_state(struct cfspi *cfspi, int state);
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int cfspi_xmitfrm(struct cfspi *cfspi, u8 *buf, size_t len);
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int cfspi_xmitlen(struct cfspi *cfspi);
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int cfspi_rxfrm(struct cfspi *cfspi, u8 *buf, size_t len);
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int cfspi_spi_remove(struct platform_device *pdev);
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int cfspi_spi_probe(struct platform_device *pdev);
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int cfspi_xmitfrm(struct cfspi *cfspi, u8 *buf, size_t len);
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int cfspi_xmitlen(struct cfspi *cfspi);
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int cfspi_rxfrm(struct cfspi *cfspi, u8 *buf, size_t len);
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void cfspi_xfer(struct work_struct *work);
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#endif /* CAIF_SPI_H_ */
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