64 lines
3.0 KiB
Plaintext
64 lines
3.0 KiB
Plaintext
Spreadtrum ADI controller
|
|
|
|
ADI is the abbreviation of Anolog-Digital interface, which is used to access
|
|
analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
|
|
framework for its hardware implementation is alike to SPI bus and its timing
|
|
is compatile to SPI timing.
|
|
|
|
ADI controller has 50 channels including 2 software read/write channels and
|
|
48 hardware channels to access analog chip. For 2 software read/write channels,
|
|
users should set ADI registers to access analog chip. For hardware channels,
|
|
we can configure them to allow other hardware components to use it independently,
|
|
which means we can just link one analog chip address to one hardware channel,
|
|
then users can access the mapped analog chip address by this hardware channel
|
|
triggered by hardware components instead of ADI software channels.
|
|
|
|
Thus we introduce one property named "sprd,hw-channels" to configure hardware
|
|
channels, the first value specifies the hardware channel id which is used to
|
|
transfer data triggered by hardware automatically, and the second value specifies
|
|
the analog chip address where user want to access by hardware components.
|
|
|
|
Since we have multi-subsystems will use unique ADI to access analog chip, when
|
|
one system is reading/writing data by ADI software channels, that should be under
|
|
one hardware spinlock protection to prevent other systems from reading/writing
|
|
data by ADI software channels at the same time, or two parallel routine of setting
|
|
ADI registers will make ADI controller registers chaos to lead incorrect results.
|
|
Then we need one hardware spinlock to synchronize between the multiple subsystems.
|
|
|
|
The new version ADI controller supplies multiple master channels for different
|
|
subsystem accessing, that means no need to add hardware spinlock to synchronize,
|
|
thus change the hardware spinlock support to be optional to keep backward
|
|
compatibility.
|
|
|
|
Required properties:
|
|
- compatible: Should be "sprd,sc9860-adi".
|
|
- reg: Offset and length of ADI-SPI controller register space.
|
|
- #address-cells: Number of cells required to define a chip select address
|
|
on the ADI-SPI bus. Should be set to 1.
|
|
- #size-cells: Size of cells required to define a chip select address size
|
|
on the ADI-SPI bus. Should be set to 0.
|
|
|
|
Optional properties:
|
|
- hwlocks: Reference to a phandle of a hwlock provider node.
|
|
- hwlock-names: Reference to hwlock name strings defined in the same order
|
|
as the hwlocks, should be "adi".
|
|
- sprd,hw-channels: This is an array of channel values up to 49 channels.
|
|
The first value specifies the hardware channel id which is used to
|
|
transfer data triggered by hardware automatically, and the second
|
|
value specifies the analog chip address where user want to access
|
|
by hardware components.
|
|
|
|
SPI slave nodes must be children of the SPI controller node and can contain
|
|
properties described in Documentation/devicetree/bindings/spi/spi-bus.txt.
|
|
|
|
Example:
|
|
adi_bus: spi@40030000 {
|
|
compatible = "sprd,sc9860-adi";
|
|
reg = <0 0x40030000 0 0x10000>;
|
|
hwlocks = <&hwlock1 0>;
|
|
hwlock-names = "adi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
sprd,hw-channels = <30 0x8c20>;
|
|
};
|