178 lines
3.8 KiB
C
178 lines
3.8 KiB
C
/*
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* sc-ip22.c: Indy cache management functions.
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*
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* Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
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* derived from r4xx0.c by David S. Miller (dm@engr.sgi.com).
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/bcache.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/system.h>
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#include <asm/bootinfo.h>
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#include <asm/sgi/ip22.h>
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#include <asm/sgi/mc.h>
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/* Secondary cache size in bytes, if present. */
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static unsigned long scache_size;
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#undef DEBUG_CACHE
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#define SC_SIZE 0x00080000
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#define SC_LINE 32
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#define CI_MASK (SC_SIZE - SC_LINE)
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#define SC_INDEX(n) ((n) & CI_MASK)
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static inline void indy_sc_wipe(unsigned long first, unsigned long last)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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".set\tpush\t\t\t# indy_sc_wipe\n\t"
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".set\tnoreorder\n\t"
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".set\tmips3\n\t"
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".set\tnoat\n\t"
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"mfc0\t%2, $12\n\t"
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"li\t$1, 0x80\t\t\t# Go 64 bit\n\t"
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"mtc0\t$1, $12\n\t"
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"dli\t$1, 0x9000000080000000\n\t"
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"or\t%0, $1\t\t\t# first line to flush\n\t"
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"or\t%1, $1\t\t\t# last line to flush\n\t"
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".set\tat\n\t"
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"1:\tsw\t$0, 0(%0)\n\t"
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"bne\t%0, %1, 1b\n\t"
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" daddu\t%0, 32\n\t"
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"mtc0\t%2, $12\t\t\t# Back to 32 bit\n\t"
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"nop; nop; nop; nop;\n\t"
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".set\tpop"
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: "=r" (first), "=r" (last), "=&r" (tmp)
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: "0" (first), "1" (last));
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}
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static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size)
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{
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unsigned long first_line, last_line;
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unsigned long flags;
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#ifdef DEBUG_CACHE
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printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size);
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#endif
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/* Catch bad driver code */
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BUG_ON(size == 0);
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/* Which lines to flush? */
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first_line = SC_INDEX(addr);
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last_line = SC_INDEX(addr + size - 1);
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local_irq_save(flags);
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if (first_line <= last_line) {
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indy_sc_wipe(first_line, last_line);
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goto out;
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}
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indy_sc_wipe(first_line, SC_SIZE - SC_LINE);
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indy_sc_wipe(0, last_line);
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out:
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local_irq_restore(flags);
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}
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static void indy_sc_enable(void)
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{
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unsigned long addr, tmp1, tmp2;
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/* This is really cool... */
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#ifdef DEBUG_CACHE
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printk("Enabling R4600 SCACHE\n");
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#endif
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__asm__ __volatile__(
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".set\tpush\n\t"
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".set\tnoreorder\n\t"
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".set\tmips3\n\t"
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"mfc0\t%2, $12\n\t"
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"nop; nop; nop; nop;\n\t"
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"li\t%1, 0x80\n\t"
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"mtc0\t%1, $12\n\t"
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"nop; nop; nop; nop;\n\t"
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"li\t%0, 0x1\n\t"
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"dsll\t%0, 31\n\t"
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"lui\t%1, 0x9000\n\t"
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"dsll32\t%1, 0\n\t"
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"or\t%0, %1, %0\n\t"
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"sb\t$0, 0(%0)\n\t"
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"mtc0\t$0, $12\n\t"
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"nop; nop; nop; nop;\n\t"
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"mtc0\t%2, $12\n\t"
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"nop; nop; nop; nop;\n\t"
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".set\tpop"
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: "=r" (tmp1), "=r" (tmp2), "=r" (addr));
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}
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static void indy_sc_disable(void)
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{
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unsigned long tmp1, tmp2, tmp3;
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#ifdef DEBUG_CACHE
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printk("Disabling R4600 SCACHE\n");
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#endif
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__asm__ __volatile__(
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".set\tpush\n\t"
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".set\tnoreorder\n\t"
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".set\tmips3\n\t"
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"li\t%0, 0x1\n\t"
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"dsll\t%0, 31\n\t"
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"lui\t%1, 0x9000\n\t"
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"dsll32\t%1, 0\n\t"
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"or\t%0, %1, %0\n\t"
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"mfc0\t%2, $12\n\t"
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"nop; nop; nop; nop\n\t"
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"li\t%1, 0x80\n\t"
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"mtc0\t%1, $12\n\t"
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"nop; nop; nop; nop\n\t"
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"sh\t$0, 0(%0)\n\t"
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"mtc0\t$0, $12\n\t"
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"nop; nop; nop; nop\n\t"
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"mtc0\t%2, $12\n\t"
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"nop; nop; nop; nop\n\t"
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".set\tpop"
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: "=r" (tmp1), "=r" (tmp2), "=r" (tmp3));
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}
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static inline int __init indy_sc_probe(void)
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{
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unsigned int size = ip22_eeprom_read(&sgimc->eeprom, 17);
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if (size == 0)
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return 0;
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size <<= PAGE_SHIFT;
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printk(KERN_INFO "R4600/R5000 SCACHE size %dK, linesize 32 bytes.\n",
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size >> 10);
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scache_size = size;
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return 1;
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}
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/* XXX Check with wje if the Indy caches can differenciate between
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writeback + invalidate and just invalidate. */
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struct bcache_ops indy_sc_ops = {
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.bc_enable = indy_sc_enable,
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.bc_disable = indy_sc_disable,
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.bc_wback_inv = indy_sc_wback_invalidate,
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.bc_inv = indy_sc_wback_invalidate
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};
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void __cpuinit indy_sc_init(void)
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{
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if (indy_sc_probe()) {
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indy_sc_enable();
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bcops = &indy_sc_ops;
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}
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}
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