OpenCloudOS-Kernel/arch/arm/include
Uwe Kleine-König 3f18b1bf59 ARM: make isa_mode macro more robust and fix for v7-M
The definition of isa_mode hardcodes the values to shift PSR_J_BIT and
PSR_T_BIT to move them to bits 1 and 0 respectively. Instead use __ffs to
calculate the shift from the #define already used for masking.

This is relevant on v7-M as there PSR_T_BIT is 0x01000000 instead of
0x00000020 for V7-[AR] and earlier. Because of that isa_mode produced
values >= 0x80000 which are unsuitable to index into isa_modes[4] there
and so made __show_regs read from undefined memory which resulted in
hangs and crashes.

Moreover isa_mode is wrong for v7-M even after this robustness fix as
there is no J-bit in the PSR register. So hardcode isa_mode to "Thumb"
for v7-M.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2014-02-03 11:46:39 +01:00
..
asm ARM: make isa_mode macro more robust and fix for v7-M 2014-02-03 11:46:39 +01:00
debug i.MX SoC changes for 3.14: 2014-01-02 12:10:12 -08:00
uapi/asm First round of KVM updates for 3.14; PPC parts will come next week. 2014-01-22 21:40:43 -08:00