469 lines
11 KiB
C
469 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
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* which contain:
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*
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* Author: Nicolas Pitre
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* Created: Dec 02, 2004
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* Copyright: MontaVista Software Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <linux/soc/pxa/cpu.h>
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#include <sound/pxa2xx-lib.h>
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#include <linux/platform_data/asoc-pxa.h>
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#include "pxa2xx-ac97-regs.h"
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static DEFINE_MUTEX(car_mutex);
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static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
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static volatile long gsr_bits;
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static struct clk *ac97_clk;
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static struct clk *ac97conf_clk;
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static int reset_gpio;
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static void __iomem *ac97_reg_base;
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extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
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/*
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* Beware PXA27x bugs:
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*
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* o Slot 12 read from modem space will hang controller.
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* o CDONE, SDONE interrupt fails after any slot 12 IO.
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*
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* We therefore have an hybrid approach for waiting on SDONE (interrupt or
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* 1 jiffy timeout if interrupt never comes).
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*/
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int pxa2xx_ac97_read(int slot, unsigned short reg)
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{
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int val = -ENODEV;
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u32 __iomem *reg_addr;
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if (slot > 0)
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return -ENODEV;
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mutex_lock(&car_mutex);
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/* set up primary or secondary codec space */
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if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
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reg_addr = ac97_reg_base +
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(slot ? SMC_REG_BASE : PMC_REG_BASE);
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else
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reg_addr = ac97_reg_base +
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(slot ? SAC_REG_BASE : PAC_REG_BASE);
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reg_addr += (reg >> 1);
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/* start read access across the ac97 link */
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writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
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gsr_bits = 0;
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val = (readl(reg_addr) & 0xffff);
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if (reg == AC97_GPIO_STATUS)
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goto out;
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if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1) <= 0 &&
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!((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE)) {
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printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
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__func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
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val = -ETIMEDOUT;
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goto out;
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}
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/* valid data now */
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writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
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gsr_bits = 0;
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val = (readl(reg_addr) & 0xffff);
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/* but we've just started another cycle... */
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wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1);
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out: mutex_unlock(&car_mutex);
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return val;
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
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int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val)
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{
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u32 __iomem *reg_addr;
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int ret = 0;
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mutex_lock(&car_mutex);
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/* set up primary or secondary codec space */
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if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
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reg_addr = ac97_reg_base +
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(slot ? SMC_REG_BASE : PMC_REG_BASE);
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else
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reg_addr = ac97_reg_base +
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(slot ? SAC_REG_BASE : PAC_REG_BASE);
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reg_addr += (reg >> 1);
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writel(GSR_CDONE | GSR_SDONE, ac97_reg_base + GSR);
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gsr_bits = 0;
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writel(val, reg_addr);
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if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE, 1) <= 0 &&
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!((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE)) {
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printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
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__func__, reg, readl(ac97_reg_base + GSR) | gsr_bits);
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ret = -EIO;
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}
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mutex_unlock(&car_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
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#ifdef CONFIG_PXA25x
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static inline void pxa_ac97_warm_pxa25x(void)
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{
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gsr_bits = 0;
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writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
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}
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static inline void pxa_ac97_cold_pxa25x(void)
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{
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writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
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writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
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gsr_bits = 0;
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writel(GCR_COLD_RST, ac97_reg_base + GCR);
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}
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#endif
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#ifdef CONFIG_PXA27x
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static inline void pxa_ac97_warm_pxa27x(void)
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{
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gsr_bits = 0;
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/* warm reset broken on Bulverde, so manually keep AC97 reset high */
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pxa27x_configure_ac97reset(reset_gpio, true);
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udelay(10);
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writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
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pxa27x_configure_ac97reset(reset_gpio, false);
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udelay(500);
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}
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static inline void pxa_ac97_cold_pxa27x(void)
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{
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writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
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writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
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gsr_bits = 0;
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/* PXA27x Developers Manual section 13.5.2.2.1 */
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clk_prepare_enable(ac97conf_clk);
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udelay(5);
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clk_disable_unprepare(ac97conf_clk);
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writel(GCR_COLD_RST | GCR_WARM_RST, ac97_reg_base + GCR);
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}
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#endif
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#ifdef CONFIG_PXA3xx
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static inline void pxa_ac97_warm_pxa3xx(void)
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{
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gsr_bits = 0;
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/* Can't use interrupts */
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writel(readl(ac97_reg_base + GCR) | (GCR_WARM_RST), ac97_reg_base + GCR);
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}
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static inline void pxa_ac97_cold_pxa3xx(void)
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{
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/* Hold CLKBPB for 100us */
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writel(0, ac97_reg_base + GCR);
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writel(GCR_CLKBPB, ac97_reg_base + GCR);
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udelay(100);
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writel(0, ac97_reg_base + GCR);
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writel(readl(ac97_reg_base + GCR) & ( GCR_COLD_RST), ac97_reg_base + GCR); /* clear everything but nCRST */
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writel(readl(ac97_reg_base + GCR) & (~GCR_COLD_RST), ac97_reg_base + GCR); /* then assert nCRST */
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gsr_bits = 0;
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/* Can't use interrupts on PXA3xx */
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writel(readl(ac97_reg_base + GCR) & (~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN)), ac97_reg_base + GCR);
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writel(GCR_WARM_RST | GCR_COLD_RST, ac97_reg_base + GCR);
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}
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#endif
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bool pxa2xx_ac97_try_warm_reset(void)
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{
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unsigned long gsr;
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unsigned int timeout = 100;
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#ifdef CONFIG_PXA25x
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if (cpu_is_pxa25x())
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pxa_ac97_warm_pxa25x();
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else
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#endif
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#ifdef CONFIG_PXA27x
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if (cpu_is_pxa27x())
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pxa_ac97_warm_pxa27x();
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else
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#endif
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#ifdef CONFIG_PXA3xx
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if (cpu_is_pxa3xx())
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pxa_ac97_warm_pxa3xx();
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else
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#endif
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snd_BUG();
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while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(1);
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gsr = readl(ac97_reg_base + GSR) | gsr_bits;
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if (!(gsr & (GSR_PCR | GSR_SCR))) {
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printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
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__func__, gsr);
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
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bool pxa2xx_ac97_try_cold_reset(void)
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{
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unsigned long gsr;
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unsigned int timeout = 1000;
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#ifdef CONFIG_PXA25x
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if (cpu_is_pxa25x())
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pxa_ac97_cold_pxa25x();
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else
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#endif
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#ifdef CONFIG_PXA27x
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if (cpu_is_pxa27x())
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pxa_ac97_cold_pxa27x();
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else
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#endif
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#ifdef CONFIG_PXA3xx
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if (cpu_is_pxa3xx())
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pxa_ac97_cold_pxa3xx();
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else
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#endif
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snd_BUG();
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while (!((readl(ac97_reg_base + GSR) | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
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mdelay(1);
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gsr = readl(ac97_reg_base + GSR) | gsr_bits;
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if (!(gsr & (GSR_PCR | GSR_SCR))) {
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printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
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__func__, gsr);
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return false;
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}
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return true;
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
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void pxa2xx_ac97_finish_reset(void)
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{
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u32 gcr = readl(ac97_reg_base + GCR);
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gcr &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
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gcr |= GCR_SDONE_IE|GCR_CDONE_IE;
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writel(gcr, ac97_reg_base + GCR);
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
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static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
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{
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long status;
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status = readl(ac97_reg_base + GSR);
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if (status) {
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writel(status, ac97_reg_base + GSR);
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gsr_bits |= status;
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wake_up(&gsr_wq);
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/* Although we don't use those we still need to clear them
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since they tend to spuriously trigger when MMC is used
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(hardware bug? go figure)... */
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if (cpu_is_pxa27x()) {
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writel(MISR_EOC, ac97_reg_base + MISR);
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writel(PISR_EOC, ac97_reg_base + PISR);
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writel(MCSR_EOC, ac97_reg_base + MCSR);
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}
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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#ifdef CONFIG_PM
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int pxa2xx_ac97_hw_suspend(void)
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{
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writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
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clk_disable_unprepare(ac97_clk);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
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int pxa2xx_ac97_hw_resume(void)
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{
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clk_prepare_enable(ac97_clk);
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return 0;
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
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#endif
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int pxa2xx_ac97_hw_probe(struct platform_device *dev)
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{
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int ret;
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int irq;
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pxa2xx_audio_ops_t *pdata = dev->dev.platform_data;
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ac97_reg_base = devm_platform_ioremap_resource(dev, 0);
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if (IS_ERR(ac97_reg_base)) {
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dev_err(&dev->dev, "Missing MMIO resource\n");
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return PTR_ERR(ac97_reg_base);
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}
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if (pdata) {
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switch (pdata->reset_gpio) {
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case 95:
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case 113:
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reset_gpio = pdata->reset_gpio;
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break;
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case 0:
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reset_gpio = 113;
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break;
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case -1:
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break;
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default:
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dev_err(&dev->dev, "Invalid reset GPIO %d\n",
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pdata->reset_gpio);
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}
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} else if (!pdata && dev->dev.of_node) {
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pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return -ENOMEM;
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pdata->reset_gpio = of_get_named_gpio(dev->dev.of_node,
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"reset-gpios", 0);
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if (pdata->reset_gpio == -ENOENT)
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pdata->reset_gpio = -1;
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else if (pdata->reset_gpio < 0)
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return pdata->reset_gpio;
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reset_gpio = pdata->reset_gpio;
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} else {
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if (cpu_is_pxa27x())
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reset_gpio = 113;
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}
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if (cpu_is_pxa27x()) {
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/*
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* This gpio is needed for a work-around to a bug in the ac97
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* controller during warm reset. The direction and level is set
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* here so that it is an output driven high when switching from
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* AC97_nRESET alt function to generic gpio.
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*/
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ret = gpio_request_one(reset_gpio, GPIOF_OUT_INIT_HIGH,
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"pxa27x ac97 reset");
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if (ret < 0) {
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pr_err("%s: gpio_request_one() failed: %d\n",
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__func__, ret);
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goto err_conf;
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}
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pxa27x_configure_ac97reset(reset_gpio, false);
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ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
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if (IS_ERR(ac97conf_clk)) {
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ret = PTR_ERR(ac97conf_clk);
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ac97conf_clk = NULL;
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goto err_conf;
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}
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}
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ac97_clk = clk_get(&dev->dev, "AC97CLK");
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if (IS_ERR(ac97_clk)) {
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ret = PTR_ERR(ac97_clk);
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ac97_clk = NULL;
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goto err_clk;
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}
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ret = clk_prepare_enable(ac97_clk);
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if (ret)
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goto err_clk2;
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irq = platform_get_irq(dev, 0);
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if (irq < 0) {
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ret = irq;
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goto err_irq;
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}
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ret = request_irq(irq, pxa2xx_ac97_irq, 0, "AC97", NULL);
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if (ret < 0)
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goto err_irq;
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return 0;
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err_irq:
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writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
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err_clk2:
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clk_put(ac97_clk);
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ac97_clk = NULL;
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err_clk:
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if (ac97conf_clk) {
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clk_put(ac97conf_clk);
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ac97conf_clk = NULL;
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}
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err_conf:
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return ret;
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
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void pxa2xx_ac97_hw_remove(struct platform_device *dev)
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{
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if (cpu_is_pxa27x())
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gpio_free(reset_gpio);
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writel(readl(ac97_reg_base + GCR) | (GCR_ACLINK_OFF), ac97_reg_base + GCR);
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free_irq(platform_get_irq(dev, 0), NULL);
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if (ac97conf_clk) {
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clk_put(ac97conf_clk);
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ac97conf_clk = NULL;
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}
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clk_disable_unprepare(ac97_clk);
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clk_put(ac97_clk);
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ac97_clk = NULL;
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
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u32 pxa2xx_ac97_read_modr(void)
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{
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if (!ac97_reg_base)
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return 0;
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return readl(ac97_reg_base + MODR);
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_read_modr);
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u32 pxa2xx_ac97_read_misr(void)
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{
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if (!ac97_reg_base)
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return 0;
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return readl(ac97_reg_base + MISR);
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}
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EXPORT_SYMBOL_GPL(pxa2xx_ac97_read_misr);
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MODULE_AUTHOR("Nicolas Pitre");
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MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
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MODULE_LICENSE("GPL");
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