619 lines
17 KiB
ArmAsm
619 lines
17 KiB
ArmAsm
/*
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* arch/ppc/kernel/hashtable.S
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*
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* $Id: hashtable.S,v 1.6 1999/10/08 01:56:15 paulus Exp $
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*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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*
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* This file contains low-level assembler routines for managing
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* the PowerPC MMU hash table. (PPC 8xx processors don't use a
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* hash table, so this file is not used on them.)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_SMP
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.comm mmu_hash_lock,4
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#endif /* CONFIG_SMP */
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/*
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* Sync CPUs with hash_page taking & releasing the hash
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* table lock
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*/
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#ifdef CONFIG_SMP
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.text
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_GLOBAL(hash_page_sync)
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lis r8,mmu_hash_lock@h
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ori r8,r8,mmu_hash_lock@l
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lis r0,0x0fff
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b 10f
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11: lwz r6,0(r8)
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cmpwi 0,r6,0
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bne 11b
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10: lwarx r6,0,r8
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cmpwi 0,r6,0
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bne- 11b
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stwcx. r0,0,r8
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bne- 10b
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isync
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eieio
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li r0,0
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stw r0,0(r8)
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blr
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#endif
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/*
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* Load a PTE into the hash table, if possible.
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* The address is in r4, and r3 contains an access flag:
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* _PAGE_RW (0x400) if a write.
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* r9 contains the SRR1 value, from which we use the MSR_PR bit.
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* SPRG3 contains the physical address of the current task's thread.
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*
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* Returns to the caller if the access is illegal or there is no
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* mapping for the address. Otherwise it places an appropriate PTE
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* in the hash table and returns from the exception.
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* Uses r0, r3 - r8, ctr, lr.
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*/
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.text
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_GLOBAL(hash_page)
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#ifdef CONFIG_PPC64BRIDGE
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mfmsr r0
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clrldi r0,r0,1 /* make sure it's in 32-bit mode */
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MTMSRD(r0)
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isync
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#endif
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tophys(r7,0) /* gets -KERNELBASE into r7 */
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#ifdef CONFIG_SMP
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addis r8,r7,mmu_hash_lock@h
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ori r8,r8,mmu_hash_lock@l
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lis r0,0x0fff
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b 10f
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11: lwz r6,0(r8)
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cmpwi 0,r6,0
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bne 11b
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10: lwarx r6,0,r8
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cmpwi 0,r6,0
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bne- 11b
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stwcx. r0,0,r8
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bne- 10b
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isync
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#endif
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/* Get PTE (linux-style) and check access */
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lis r0,KERNELBASE@h /* check if kernel address */
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cmplw 0,r4,r0
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mfspr r8,SPRN_SPRG3 /* current task's THREAD (phys) */
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ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
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lwz r5,PGDIR(r8) /* virt page-table root */
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blt+ 112f /* assume user more likely */
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lis r5,swapper_pg_dir@ha /* if kernel address, use */
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addi r5,r5,swapper_pg_dir@l /* kernel page table */
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rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
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112: add r5,r5,r7 /* convert to phys addr */
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rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
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lwz r8,0(r5) /* get pmd entry */
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rlwinm. r8,r8,0,0,19 /* extract address of pte page */
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#ifdef CONFIG_SMP
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beq- hash_page_out /* return if no mapping */
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#else
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/* XXX it seems like the 601 will give a machine fault on the
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rfi if its alignment is wrong (bottom 4 bits of address are
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8 or 0xc) and we have had a not-taken conditional branch
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to the address following the rfi. */
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beqlr-
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#endif
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rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
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rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
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ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
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/*
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* Update the linux PTE atomically. We do the lwarx up-front
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* because almost always, there won't be a permission violation
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* and there won't already be an HPTE, and thus we will have
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* to update the PTE to set _PAGE_HASHPTE. -- paulus.
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*/
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retry:
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lwarx r6,0,r8 /* get linux-style pte */
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andc. r5,r3,r6 /* check access & ~permission */
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#ifdef CONFIG_SMP
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bne- hash_page_out /* return if access not permitted */
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#else
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bnelr-
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#endif
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or r5,r0,r6 /* set accessed/dirty bits */
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stwcx. r5,0,r8 /* attempt to update PTE */
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bne- retry /* retry if someone got there first */
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mfsrin r3,r4 /* get segment reg for segment */
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mfctr r0
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stw r0,_CTR(r11)
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bl create_hpte /* add the hash table entry */
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#ifdef CONFIG_SMP
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eieio
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addis r8,r7,mmu_hash_lock@ha
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li r0,0
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stw r0,mmu_hash_lock@l(r8)
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#endif
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/* Return from the exception */
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lwz r5,_CTR(r11)
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mtctr r5
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lwz r0,GPR0(r11)
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lwz r7,GPR7(r11)
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lwz r8,GPR8(r11)
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b fast_exception_return
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#ifdef CONFIG_SMP
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hash_page_out:
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eieio
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addis r8,r7,mmu_hash_lock@ha
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li r0,0
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stw r0,mmu_hash_lock@l(r8)
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blr
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#endif /* CONFIG_SMP */
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/*
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* Add an entry for a particular page to the hash table.
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*
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* add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
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*
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* We assume any necessary modifications to the pte (e.g. setting
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* the accessed bit) have already been done and that there is actually
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* a hash table in use (i.e. we're not on a 603).
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*/
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_GLOBAL(add_hash_page)
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mflr r0
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stw r0,4(r1)
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/* Convert context and va to VSID */
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mulli r3,r3,897*16 /* multiply context by context skew */
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rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
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mulli r0,r0,0x111 /* multiply by ESID skew */
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add r3,r3,r0 /* note create_hpte trims to 24 bits */
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#ifdef CONFIG_SMP
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rlwinm r8,r1,0,0,18 /* use cpu number to make tag */
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lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */
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oris r8,r8,12
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#endif /* CONFIG_SMP */
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/*
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* We disable interrupts here, even on UP, because we don't
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* want to race with hash_page, and because we want the
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* _PAGE_HASHPTE bit to be a reliable indication of whether
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* the HPTE exists (or at least whether one did once).
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* We also turn off the MMU for data accesses so that we
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* we can't take a hash table miss (assuming the code is
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* covered by a BAT). -- paulus
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*/
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear MSR_DR */
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mtmsr r0
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SYNC_601
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isync
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tophys(r7,0)
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#ifdef CONFIG_SMP
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addis r9,r7,mmu_hash_lock@ha
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addi r9,r9,mmu_hash_lock@l
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10: lwarx r0,0,r9 /* take the mmu_hash_lock */
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cmpi 0,r0,0
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bne- 11f
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stwcx. r8,0,r9
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beq+ 12f
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11: lwz r0,0(r9)
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cmpi 0,r0,0
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beq 10b
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b 11b
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12: isync
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#endif
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/*
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* Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
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* If _PAGE_HASHPTE was already set, we don't replace the existing
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* HPTE, so we just unlock and return.
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*/
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mr r8,r5
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rlwimi r8,r4,22,20,29
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1: lwarx r6,0,r8
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andi. r0,r6,_PAGE_HASHPTE
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bne 9f /* if HASHPTE already set, done */
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ori r5,r6,_PAGE_HASHPTE
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stwcx. r5,0,r8
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bne- 1b
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bl create_hpte
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9:
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#ifdef CONFIG_SMP
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eieio
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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#endif
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/* reenable interrupts and DR */
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mtmsr r10
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SYNC_601
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isync
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lwz r0,4(r1)
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mtlr r0
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blr
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/*
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* This routine adds a hardware PTE to the hash table.
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* It is designed to be called with the MMU either on or off.
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* r3 contains the VSID, r4 contains the virtual address,
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* r5 contains the linux PTE, r6 contains the old value of the
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* linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
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* offset to be added to addresses (0 if the MMU is on,
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* -KERNELBASE if it is off).
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* On SMP, the caller should have the mmu_hash_lock held.
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* We assume that the caller has (or will) set the _PAGE_HASHPTE
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* bit in the linux PTE in memory. The value passed in r6 should
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* be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
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* this routine will skip the search for an existing HPTE.
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* This procedure modifies r0, r3 - r6, r8, cr0.
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* -- paulus.
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*
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* For speed, 4 of the instructions get patched once the size and
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* physical address of the hash table are known. These definitions
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* of Hash_base and Hash_bits below are just an example.
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*/
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Hash_base = 0xc0180000
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Hash_bits = 12 /* e.g. 256kB hash table */
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Hash_msk = (((1 << Hash_bits) - 1) * 64)
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#ifndef CONFIG_PPC64BRIDGE
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/* defines for the PTE format for 32-bit PPCs */
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#define PTE_SIZE 8
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#define PTEG_SIZE 64
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#define LG_PTEG_SIZE 6
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#define LDPTEu lwzu
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#define STPTE stw
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#define CMPPTE cmpw
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#define PTE_H 0x40
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#define PTE_V 0x80000000
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#define TST_V(r) rlwinm. r,r,0,0,0
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#define SET_V(r) oris r,r,PTE_V@h
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#define CLR_V(r,t) rlwinm r,r,0,1,31
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#else
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/* defines for the PTE format for 64-bit PPCs */
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#define PTE_SIZE 16
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#define PTEG_SIZE 128
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#define LG_PTEG_SIZE 7
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#define LDPTEu ldu
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#define STPTE std
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#define CMPPTE cmpd
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#define PTE_H 2
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#define PTE_V 1
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#define TST_V(r) andi. r,r,PTE_V
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#define SET_V(r) ori r,r,PTE_V
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#define CLR_V(r,t) li t,PTE_V; andc r,r,t
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#endif /* CONFIG_PPC64BRIDGE */
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#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
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#define HASH_RIGHT 31-LG_PTEG_SIZE
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_GLOBAL(create_hpte)
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/* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
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rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */
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rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
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and r8,r8,r0 /* writable if _RW & _DIRTY */
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rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
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rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
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ori r8,r8,0xe14 /* clear out reserved bits and M */
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andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
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BEGIN_FTR_SECTION
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ori r8,r8,_PAGE_COHERENT /* set M (coherence required) */
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END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
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/* Construct the high word of the PPC-style PTE (r5) */
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#ifndef CONFIG_PPC64BRIDGE
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rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
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rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
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#else /* CONFIG_PPC64BRIDGE */
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clrlwi r3,r3,8 /* reduce vsid to 24 bits */
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sldi r5,r3,12 /* shift vsid into position */
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rlwimi r5,r4,16,20,24 /* put in API (abbrev page index) */
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#endif /* CONFIG_PPC64BRIDGE */
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SET_V(r5) /* set V (valid) bit */
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/* Get the address of the primary PTE group in the hash table (r3) */
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_GLOBAL(hash_page_patch_A)
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addis r0,r7,Hash_base@h /* base address of hash table */
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rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
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rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
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xor r3,r3,r0 /* make primary hash */
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li r0,8 /* PTEs/group */
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/*
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* Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
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* if it is clear, meaning that the HPTE isn't there already...
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*/
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andi. r6,r6,_PAGE_HASHPTE
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beq+ 10f /* no PTE: go look for an empty slot */
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tlbie r4
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addis r4,r7,htab_hash_searches@ha
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lwz r6,htab_hash_searches@l(r4)
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addi r6,r6,1 /* count how many searches we do */
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stw r6,htab_hash_searches@l(r4)
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/* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
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mtctr r0
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addi r4,r3,-PTE_SIZE
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1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
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CMPPTE 0,r6,r5
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bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
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beq+ found_slot
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/* Search the secondary PTEG for a matching PTE */
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ori r5,r5,PTE_H /* set H (secondary hash) bit */
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_GLOBAL(hash_page_patch_B)
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xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
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xori r4,r4,(-PTEG_SIZE & 0xffff)
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addi r4,r4,-PTE_SIZE
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mtctr r0
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2: LDPTEu r6,PTE_SIZE(r4)
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CMPPTE 0,r6,r5
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bdnzf 2,2b
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beq+ found_slot
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xori r5,r5,PTE_H /* clear H bit again */
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/* Search the primary PTEG for an empty slot */
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10: mtctr r0
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addi r4,r3,-PTE_SIZE /* search primary PTEG */
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1: LDPTEu r6,PTE_SIZE(r4) /* get next PTE */
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TST_V(r6) /* test valid bit */
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bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
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beq+ found_empty
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/* update counter of times that the primary PTEG is full */
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addis r4,r7,primary_pteg_full@ha
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lwz r6,primary_pteg_full@l(r4)
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addi r6,r6,1
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stw r6,primary_pteg_full@l(r4)
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/* Search the secondary PTEG for an empty slot */
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ori r5,r5,PTE_H /* set H (secondary hash) bit */
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_GLOBAL(hash_page_patch_C)
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xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
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xori r4,r4,(-PTEG_SIZE & 0xffff)
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addi r4,r4,-PTE_SIZE
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mtctr r0
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2: LDPTEu r6,PTE_SIZE(r4)
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TST_V(r6)
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bdnzf 2,2b
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beq+ found_empty
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xori r5,r5,PTE_H /* clear H bit again */
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/*
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* Choose an arbitrary slot in the primary PTEG to overwrite.
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* Since both the primary and secondary PTEGs are full, and we
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* have no information that the PTEs in the primary PTEG are
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* more important or useful than those in the secondary PTEG,
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* and we know there is a definite (although small) speed
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* advantage to putting the PTE in the primary PTEG, we always
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* put the PTE in the primary PTEG.
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*/
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addis r4,r7,next_slot@ha
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lwz r6,next_slot@l(r4)
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addi r6,r6,PTE_SIZE
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andi. r6,r6,7*PTE_SIZE
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stw r6,next_slot@l(r4)
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add r4,r3,r6
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#ifndef CONFIG_SMP
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/* Store PTE in PTEG */
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found_empty:
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STPTE r5,0(r4)
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found_slot:
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STPTE r8,PTE_SIZE/2(r4)
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#else /* CONFIG_SMP */
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/*
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* Between the tlbie above and updating the hash table entry below,
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* another CPU could read the hash table entry and put it in its TLB.
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* There are 3 cases:
|
|
* 1. using an empty slot
|
|
* 2. updating an earlier entry to change permissions (i.e. enable write)
|
|
* 3. taking over the PTE for an unrelated address
|
|
*
|
|
* In each case it doesn't really matter if the other CPUs have the old
|
|
* PTE in their TLB. So we don't need to bother with another tlbie here,
|
|
* which is convenient as we've overwritten the register that had the
|
|
* address. :-) The tlbie above is mainly to make sure that this CPU comes
|
|
* and gets the new PTE from the hash table.
|
|
*
|
|
* We do however have to make sure that the PTE is never in an invalid
|
|
* state with the V bit set.
|
|
*/
|
|
found_empty:
|
|
found_slot:
|
|
CLR_V(r5,r0) /* clear V (valid) bit in PTE */
|
|
STPTE r5,0(r4)
|
|
sync
|
|
TLBSYNC
|
|
STPTE r8,PTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
|
|
sync
|
|
SET_V(r5)
|
|
STPTE r5,0(r4) /* finally set V bit in PTE */
|
|
#endif /* CONFIG_SMP */
|
|
|
|
sync /* make sure pte updates get to memory */
|
|
blr
|
|
|
|
.comm next_slot,4
|
|
.comm primary_pteg_full,4
|
|
.comm htab_hash_searches,4
|
|
|
|
/*
|
|
* Flush the entry for a particular page from the hash table.
|
|
*
|
|
* flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
|
|
* int count)
|
|
*
|
|
* We assume that there is a hash table in use (Hash != 0).
|
|
*/
|
|
_GLOBAL(flush_hash_pages)
|
|
tophys(r7,0)
|
|
|
|
/*
|
|
* We disable interrupts here, even on UP, because we want
|
|
* the _PAGE_HASHPTE bit to be a reliable indication of
|
|
* whether the HPTE exists (or at least whether one did once).
|
|
* We also turn off the MMU for data accesses so that we
|
|
* we can't take a hash table miss (assuming the code is
|
|
* covered by a BAT). -- paulus
|
|
*/
|
|
mfmsr r10
|
|
SYNC
|
|
rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
|
|
rlwinm r0,r0,0,28,26 /* clear MSR_DR */
|
|
mtmsr r0
|
|
SYNC_601
|
|
isync
|
|
|
|
/* First find a PTE in the range that has _PAGE_HASHPTE set */
|
|
rlwimi r5,r4,22,20,29
|
|
1: lwz r0,0(r5)
|
|
cmpwi cr1,r6,1
|
|
andi. r0,r0,_PAGE_HASHPTE
|
|
bne 2f
|
|
ble cr1,19f
|
|
addi r4,r4,0x1000
|
|
addi r5,r5,4
|
|
addi r6,r6,-1
|
|
b 1b
|
|
|
|
/* Convert context and va to VSID */
|
|
2: mulli r3,r3,897*16 /* multiply context by context skew */
|
|
rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
|
|
mulli r0,r0,0x111 /* multiply by ESID skew */
|
|
add r3,r3,r0 /* note code below trims to 24 bits */
|
|
|
|
/* Construct the high word of the PPC-style PTE (r11) */
|
|
#ifndef CONFIG_PPC64BRIDGE
|
|
rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
|
|
rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
|
|
#else /* CONFIG_PPC64BRIDGE */
|
|
clrlwi r3,r3,8 /* reduce vsid to 24 bits */
|
|
sldi r11,r3,12 /* shift vsid into position */
|
|
rlwimi r11,r4,16,20,24 /* put in API (abbrev page index) */
|
|
#endif /* CONFIG_PPC64BRIDGE */
|
|
SET_V(r11) /* set V (valid) bit */
|
|
|
|
#ifdef CONFIG_SMP
|
|
addis r9,r7,mmu_hash_lock@ha
|
|
addi r9,r9,mmu_hash_lock@l
|
|
rlwinm r8,r1,0,0,18
|
|
add r8,r8,r7
|
|
lwz r8,TI_CPU(r8)
|
|
oris r8,r8,9
|
|
10: lwarx r0,0,r9
|
|
cmpi 0,r0,0
|
|
bne- 11f
|
|
stwcx. r8,0,r9
|
|
beq+ 12f
|
|
11: lwz r0,0(r9)
|
|
cmpi 0,r0,0
|
|
beq 10b
|
|
b 11b
|
|
12: isync
|
|
#endif
|
|
|
|
/*
|
|
* Check the _PAGE_HASHPTE bit in the linux PTE. If it is
|
|
* already clear, we're done (for this pte). If not,
|
|
* clear it (atomically) and proceed. -- paulus.
|
|
*/
|
|
33: lwarx r8,0,r5 /* fetch the pte */
|
|
andi. r0,r8,_PAGE_HASHPTE
|
|
beq 8f /* done if HASHPTE is already clear */
|
|
rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
|
|
stwcx. r8,0,r5 /* update the pte */
|
|
bne- 33b
|
|
|
|
/* Get the address of the primary PTE group in the hash table (r3) */
|
|
_GLOBAL(flush_hash_patch_A)
|
|
addis r8,r7,Hash_base@h /* base address of hash table */
|
|
rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
|
|
rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
|
|
xor r8,r0,r8 /* make primary hash */
|
|
|
|
/* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
|
|
li r0,8 /* PTEs/group */
|
|
mtctr r0
|
|
addi r12,r8,-PTE_SIZE
|
|
1: LDPTEu r0,PTE_SIZE(r12) /* get next PTE */
|
|
CMPPTE 0,r0,r11
|
|
bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
|
|
beq+ 3f
|
|
|
|
/* Search the secondary PTEG for a matching PTE */
|
|
ori r11,r11,PTE_H /* set H (secondary hash) bit */
|
|
li r0,8 /* PTEs/group */
|
|
_GLOBAL(flush_hash_patch_B)
|
|
xoris r12,r8,Hash_msk>>16 /* compute secondary hash */
|
|
xori r12,r12,(-PTEG_SIZE & 0xffff)
|
|
addi r12,r12,-PTE_SIZE
|
|
mtctr r0
|
|
2: LDPTEu r0,PTE_SIZE(r12)
|
|
CMPPTE 0,r0,r11
|
|
bdnzf 2,2b
|
|
xori r11,r11,PTE_H /* clear H again */
|
|
bne- 4f /* should rarely fail to find it */
|
|
|
|
3: li r0,0
|
|
STPTE r0,0(r12) /* invalidate entry */
|
|
4: sync
|
|
tlbie r4 /* in hw tlb too */
|
|
sync
|
|
|
|
8: ble cr1,9f /* if all ptes checked */
|
|
81: addi r6,r6,-1
|
|
addi r5,r5,4 /* advance to next pte */
|
|
addi r4,r4,0x1000
|
|
lwz r0,0(r5) /* check next pte */
|
|
cmpwi cr1,r6,1
|
|
andi. r0,r0,_PAGE_HASHPTE
|
|
bne 33b
|
|
bgt cr1,81b
|
|
|
|
9:
|
|
#ifdef CONFIG_SMP
|
|
TLBSYNC
|
|
li r0,0
|
|
stw r0,0(r9) /* clear mmu_hash_lock */
|
|
#endif
|
|
|
|
19: mtmsr r10
|
|
SYNC_601
|
|
isync
|
|
blr
|