387 lines
15 KiB
C
387 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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*/
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#ifndef _EMAC_H_
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#define _EMAC_H_
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#include <linux/irqreturn.h>
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#include <linux/netdevice.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include "emac-mac.h"
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#include "emac-phy.h"
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#include "emac-sgmii.h"
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/* EMAC base register offsets */
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#define EMAC_DMA_MAS_CTRL 0x1400
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#define EMAC_IRQ_MOD_TIM_INIT 0x1408
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#define EMAC_BLK_IDLE_STS 0x140c
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#define EMAC_PHY_LINK_DELAY 0x141c
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#define EMAC_SYS_ALIV_CTRL 0x1434
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#define EMAC_MAC_CTRL 0x1480
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#define EMAC_MAC_IPGIFG_CTRL 0x1484
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#define EMAC_MAC_STA_ADDR0 0x1488
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#define EMAC_MAC_STA_ADDR1 0x148c
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#define EMAC_HASH_TAB_REG0 0x1490
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#define EMAC_HASH_TAB_REG1 0x1494
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#define EMAC_MAC_HALF_DPLX_CTRL 0x1498
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#define EMAC_MAX_FRAM_LEN_CTRL 0x149c
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#define EMAC_WOL_CTRL0 0x14a0
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#define EMAC_RSS_KEY0 0x14b0
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#define EMAC_H1TPD_BASE_ADDR_LO 0x14e0
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#define EMAC_H2TPD_BASE_ADDR_LO 0x14e4
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#define EMAC_H3TPD_BASE_ADDR_LO 0x14e8
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#define EMAC_INTER_SRAM_PART9 0x1534
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#define EMAC_DESC_CTRL_0 0x1540
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#define EMAC_DESC_CTRL_1 0x1544
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#define EMAC_DESC_CTRL_2 0x1550
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#define EMAC_DESC_CTRL_10 0x1554
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#define EMAC_DESC_CTRL_12 0x1558
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#define EMAC_DESC_CTRL_13 0x155c
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#define EMAC_DESC_CTRL_3 0x1560
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#define EMAC_DESC_CTRL_4 0x1564
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#define EMAC_DESC_CTRL_5 0x1568
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#define EMAC_DESC_CTRL_14 0x156c
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#define EMAC_DESC_CTRL_15 0x1570
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#define EMAC_DESC_CTRL_16 0x1574
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#define EMAC_DESC_CTRL_6 0x1578
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#define EMAC_DESC_CTRL_8 0x1580
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#define EMAC_DESC_CTRL_9 0x1584
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#define EMAC_DESC_CTRL_11 0x1588
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#define EMAC_TXQ_CTRL_0 0x1590
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#define EMAC_TXQ_CTRL_1 0x1594
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#define EMAC_TXQ_CTRL_2 0x1598
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#define EMAC_RXQ_CTRL_0 0x15a0
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#define EMAC_RXQ_CTRL_1 0x15a4
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#define EMAC_RXQ_CTRL_2 0x15a8
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#define EMAC_RXQ_CTRL_3 0x15ac
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#define EMAC_BASE_CPU_NUMBER 0x15b8
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#define EMAC_DMA_CTRL 0x15c0
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#define EMAC_MAILBOX_0 0x15e0
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#define EMAC_MAILBOX_5 0x15e4
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#define EMAC_MAILBOX_6 0x15e8
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#define EMAC_MAILBOX_13 0x15ec
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#define EMAC_MAILBOX_2 0x15f4
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#define EMAC_MAILBOX_3 0x15f8
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#define EMAC_INT_STATUS 0x1600
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#define EMAC_INT_MASK 0x1604
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#define EMAC_MAILBOX_11 0x160c
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#define EMAC_AXI_MAST_CTRL 0x1610
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#define EMAC_MAILBOX_12 0x1614
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#define EMAC_MAILBOX_9 0x1618
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#define EMAC_MAILBOX_10 0x161c
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#define EMAC_ATHR_HEADER_CTRL 0x1620
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#define EMAC_RXMAC_STATC_REG0 0x1700
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#define EMAC_RXMAC_STATC_REG22 0x1758
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#define EMAC_TXMAC_STATC_REG0 0x1760
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#define EMAC_TXMAC_STATC_REG24 0x17c0
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#define EMAC_CLK_GATE_CTRL 0x1814
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#define EMAC_CORE_HW_VERSION 0x1974
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#define EMAC_MISC_CTRL 0x1990
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#define EMAC_MAILBOX_7 0x19e0
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#define EMAC_MAILBOX_8 0x19e4
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#define EMAC_IDT_TABLE0 0x1b00
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#define EMAC_RXMAC_STATC_REG23 0x1bc8
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#define EMAC_RXMAC_STATC_REG24 0x1bcc
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#define EMAC_TXMAC_STATC_REG25 0x1bd0
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#define EMAC_MAILBOX_15 0x1bd4
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#define EMAC_MAILBOX_16 0x1bd8
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#define EMAC_INT1_MASK 0x1bf0
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#define EMAC_INT1_STATUS 0x1bf4
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#define EMAC_INT2_MASK 0x1bf8
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#define EMAC_INT2_STATUS 0x1bfc
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#define EMAC_INT3_MASK 0x1c00
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#define EMAC_INT3_STATUS 0x1c04
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/* EMAC_DMA_MAS_CTRL */
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#define DEV_ID_NUM_BMSK 0x7f000000
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#define DEV_ID_NUM_SHFT 24
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#define DEV_REV_NUM_BMSK 0xff0000
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#define DEV_REV_NUM_SHFT 16
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#define INT_RD_CLR_EN 0x4000
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#define IRQ_MODERATOR2_EN 0x800
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#define IRQ_MODERATOR_EN 0x400
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#define LPW_CLK_SEL 0x80
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#define LPW_STATE 0x20
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#define LPW_MODE 0x10
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#define SOFT_RST 0x1
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/* EMAC_IRQ_MOD_TIM_INIT */
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#define IRQ_MODERATOR2_INIT_BMSK 0xffff0000
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#define IRQ_MODERATOR2_INIT_SHFT 16
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#define IRQ_MODERATOR_INIT_BMSK 0xffff
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#define IRQ_MODERATOR_INIT_SHFT 0
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/* EMAC_INT_STATUS */
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#define DIS_INT BIT(31)
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#define PTP_INT BIT(30)
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#define RFD4_UR_INT BIT(29)
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#define TX_PKT_INT3 BIT(26)
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#define TX_PKT_INT2 BIT(25)
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#define TX_PKT_INT1 BIT(24)
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#define RX_PKT_INT3 BIT(19)
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#define RX_PKT_INT2 BIT(18)
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#define RX_PKT_INT1 BIT(17)
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#define RX_PKT_INT0 BIT(16)
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#define TX_PKT_INT BIT(15)
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#define TXQ_TO_INT BIT(14)
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#define GPHY_WAKEUP_INT BIT(13)
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#define GPHY_LINK_DOWN_INT BIT(12)
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#define GPHY_LINK_UP_INT BIT(11)
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#define DMAW_TO_INT BIT(10)
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#define DMAR_TO_INT BIT(9)
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#define TXF_UR_INT BIT(8)
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#define RFD3_UR_INT BIT(7)
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#define RFD2_UR_INT BIT(6)
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#define RFD1_UR_INT BIT(5)
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#define RFD0_UR_INT BIT(4)
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#define RXF_OF_INT BIT(3)
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#define SW_MAN_INT BIT(2)
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/* EMAC_MAILBOX_6 */
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#define RFD2_PROC_IDX_BMSK 0xfff0000
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#define RFD2_PROC_IDX_SHFT 16
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#define RFD2_PROD_IDX_BMSK 0xfff
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#define RFD2_PROD_IDX_SHFT 0
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/* EMAC_CORE_HW_VERSION */
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#define MAJOR_BMSK 0xf0000000
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#define MAJOR_SHFT 28
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#define MINOR_BMSK 0xfff0000
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#define MINOR_SHFT 16
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#define STEP_BMSK 0xffff
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#define STEP_SHFT 0
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/* EMAC_EMAC_WRAPPER_CSR1 */
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#define TX_INDX_FIFO_SYNC_RST BIT(23)
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#define TX_TS_FIFO_SYNC_RST BIT(22)
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#define RX_TS_FIFO2_SYNC_RST BIT(21)
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#define RX_TS_FIFO1_SYNC_RST BIT(20)
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#define TX_TS_ENABLE BIT(16)
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#define DIS_1588_CLKS BIT(11)
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#define FREQ_MODE BIT(9)
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#define ENABLE_RRD_TIMESTAMP BIT(3)
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/* EMAC_EMAC_WRAPPER_CSR2 */
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#define HDRIVE_BMSK 0x3000
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#define HDRIVE_SHFT 12
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#define SLB_EN BIT(9)
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#define PLB_EN BIT(8)
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#define WOL_EN BIT(3)
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#define PHY_RESET BIT(0)
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#define EMAC_DEV_ID 0x0040
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/* SGMII v2 per lane registers */
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#define SGMII_LN_RSM_START 0x029C
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/* SGMII v2 PHY common registers */
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#define SGMII_PHY_CMN_CTRL 0x0408
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#define SGMII_PHY_CMN_RESET_CTRL 0x0410
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/* SGMII v2 PHY registers per lane */
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#define SGMII_PHY_LN_OFFSET 0x0400
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#define SGMII_PHY_LN_LANE_STATUS 0x00DC
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#define SGMII_PHY_LN_BIST_GEN0 0x008C
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#define SGMII_PHY_LN_BIST_GEN1 0x0090
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#define SGMII_PHY_LN_BIST_GEN2 0x0094
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#define SGMII_PHY_LN_BIST_GEN3 0x0098
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#define SGMII_PHY_LN_CDR_CTRL1 0x005C
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enum emac_clk_id {
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EMAC_CLK_AXI,
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EMAC_CLK_CFG_AHB,
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EMAC_CLK_HIGH_SPEED,
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EMAC_CLK_MDIO,
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EMAC_CLK_TX,
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EMAC_CLK_RX,
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EMAC_CLK_SYS,
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EMAC_CLK_CNT
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};
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#define EMAC_LINK_SPEED_UNKNOWN 0x0
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#define EMAC_LINK_SPEED_10_HALF BIT(0)
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#define EMAC_LINK_SPEED_10_FULL BIT(1)
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#define EMAC_LINK_SPEED_100_HALF BIT(2)
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#define EMAC_LINK_SPEED_100_FULL BIT(3)
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#define EMAC_LINK_SPEED_1GB_FULL BIT(5)
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#define EMAC_MAX_SETUP_LNK_CYCLE 100
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struct emac_stats {
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/* rx */
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u64 rx_ok; /* good packets */
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u64 rx_bcast; /* good broadcast packets */
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u64 rx_mcast; /* good multicast packets */
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u64 rx_pause; /* pause packet */
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u64 rx_ctrl; /* control packets other than pause frame. */
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u64 rx_fcs_err; /* packets with bad FCS. */
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u64 rx_len_err; /* packets with length mismatch */
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u64 rx_byte_cnt; /* good bytes count (without FCS) */
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u64 rx_runt; /* runt packets */
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u64 rx_frag; /* fragment count */
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u64 rx_sz_64; /* packets that are 64 bytes */
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u64 rx_sz_65_127; /* packets that are 65-127 bytes */
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u64 rx_sz_128_255; /* packets that are 128-255 bytes */
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u64 rx_sz_256_511; /* packets that are 256-511 bytes */
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u64 rx_sz_512_1023; /* packets that are 512-1023 bytes */
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u64 rx_sz_1024_1518; /* packets that are 1024-1518 bytes */
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u64 rx_sz_1519_max; /* packets that are 1519-MTU bytes*/
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u64 rx_sz_ov; /* packets that are >MTU bytes (truncated) */
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u64 rx_rxf_ov; /* packets dropped due to RX FIFO overflow */
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u64 rx_align_err; /* alignment errors */
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u64 rx_bcast_byte_cnt; /* broadcast packets byte count (without FCS) */
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u64 rx_mcast_byte_cnt; /* multicast packets byte count (without FCS) */
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u64 rx_err_addr; /* packets dropped due to address filtering */
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u64 rx_crc_align; /* CRC align errors */
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u64 rx_jabbers; /* jabbers */
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/* tx */
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u64 tx_ok; /* good packets */
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u64 tx_bcast; /* good broadcast packets */
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u64 tx_mcast; /* good multicast packets */
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u64 tx_pause; /* pause packets */
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u64 tx_exc_defer; /* packets with excessive deferral */
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u64 tx_ctrl; /* control packets other than pause frame */
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u64 tx_defer; /* packets that are deferred. */
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u64 tx_byte_cnt; /* good bytes count (without FCS) */
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u64 tx_sz_64; /* packets that are 64 bytes */
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u64 tx_sz_65_127; /* packets that are 65-127 bytes */
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u64 tx_sz_128_255; /* packets that are 128-255 bytes */
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u64 tx_sz_256_511; /* packets that are 256-511 bytes */
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u64 tx_sz_512_1023; /* packets that are 512-1023 bytes */
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u64 tx_sz_1024_1518; /* packets that are 1024-1518 bytes */
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u64 tx_sz_1519_max; /* packets that are 1519-MTU bytes */
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u64 tx_1_col; /* packets single prior collision */
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u64 tx_2_col; /* packets with multiple prior collisions */
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u64 tx_late_col; /* packets with late collisions */
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u64 tx_abort_col; /* packets aborted due to excess collisions */
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u64 tx_underrun; /* packets aborted due to FIFO underrun */
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u64 tx_rd_eop; /* count of reads beyond EOP */
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u64 tx_len_err; /* packets with length mismatch */
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u64 tx_trunc; /* packets truncated due to size >MTU */
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u64 tx_bcast_byte; /* broadcast packets byte count (without FCS) */
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u64 tx_mcast_byte; /* multicast packets byte count (without FCS) */
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u64 tx_col; /* collisions */
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spinlock_t lock; /* prevent multiple simultaneous readers */
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};
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/* RSS hstype Definitions */
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#define EMAC_RSS_HSTYP_IPV4_EN 0x00000001
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#define EMAC_RSS_HSTYP_TCP4_EN 0x00000002
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#define EMAC_RSS_HSTYP_IPV6_EN 0x00000004
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#define EMAC_RSS_HSTYP_TCP6_EN 0x00000008
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#define EMAC_RSS_HSTYP_ALL_EN (\
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EMAC_RSS_HSTYP_IPV4_EN |\
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EMAC_RSS_HSTYP_TCP4_EN |\
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EMAC_RSS_HSTYP_IPV6_EN |\
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EMAC_RSS_HSTYP_TCP6_EN)
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#define EMAC_VLAN_TO_TAG(_vlan, _tag) \
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(_tag = ((((_vlan) >> 8) & 0xFF) | (((_vlan) & 0xFF) << 8)))
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#define EMAC_TAG_TO_VLAN(_tag, _vlan) \
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(_vlan = ((((_tag) >> 8) & 0xFF) | (((_tag) & 0xFF) << 8)))
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#define EMAC_DEF_RX_BUF_SIZE 1536
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#define EMAC_MAX_JUMBO_PKT_SIZE (9 * 1024)
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#define EMAC_MAX_TX_OFFLOAD_THRESH (9 * 1024)
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#define EMAC_MAX_ETH_FRAME_SIZE EMAC_MAX_JUMBO_PKT_SIZE
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#define EMAC_MIN_ETH_FRAME_SIZE 68
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#define EMAC_DEF_TX_QUEUES 1
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#define EMAC_DEF_RX_QUEUES 1
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#define EMAC_MIN_TX_DESCS 128
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#define EMAC_MIN_RX_DESCS 128
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#define EMAC_MAX_TX_DESCS 16383
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#define EMAC_MAX_RX_DESCS 2047
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#define EMAC_DEF_TX_DESCS 512
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#define EMAC_DEF_RX_DESCS 256
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#define EMAC_DEF_RX_IRQ_MOD 250
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#define EMAC_DEF_TX_IRQ_MOD 250
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#define EMAC_WATCHDOG_TIME (5 * HZ)
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/* by default check link every 4 seconds */
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#define EMAC_TRY_LINK_TIMEOUT (4 * HZ)
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/* emac_irq per-device (per-adapter) irq properties.
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* @irq: irq number.
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* @mask mask to use over status register.
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*/
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struct emac_irq {
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unsigned int irq;
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u32 mask;
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};
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/* The device's main data structure */
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struct emac_adapter {
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struct net_device *netdev;
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struct mii_bus *mii_bus;
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struct phy_device *phydev;
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void __iomem *base;
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void __iomem *csr;
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struct emac_sgmii phy;
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struct emac_stats stats;
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struct emac_irq irq;
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struct clk *clk[EMAC_CLK_CNT];
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/* All Descriptor memory */
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struct emac_ring_header ring_header;
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struct emac_tx_queue tx_q;
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struct emac_rx_queue rx_q;
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unsigned int tx_desc_cnt;
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unsigned int rx_desc_cnt;
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unsigned int rrd_size; /* in quad words */
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unsigned int rfd_size; /* in quad words */
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unsigned int tpd_size; /* in quad words */
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unsigned int rxbuf_size;
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/* Flow control / pause frames support. If automatic=True, do whatever
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* the PHY does. Otherwise, use tx_flow_control and rx_flow_control.
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*/
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bool automatic;
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bool tx_flow_control;
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bool rx_flow_control;
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/* True == use single-pause-frame mode. */
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bool single_pause_mode;
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/* Ring parameter */
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u8 tpd_burst;
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u8 rfd_burst;
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unsigned int dmaw_dly_cnt;
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unsigned int dmar_dly_cnt;
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enum emac_dma_req_block dmar_block;
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enum emac_dma_req_block dmaw_block;
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enum emac_dma_order dma_order;
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u32 irq_mod;
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u32 preamble;
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struct work_struct work_thread;
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u16 msg_enable;
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struct mutex reset_lock;
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};
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int emac_reinit_locked(struct emac_adapter *adpt);
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void emac_reg_update32(void __iomem *addr, u32 mask, u32 val);
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void emac_set_ethtool_ops(struct net_device *netdev);
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void emac_update_hw_stats(struct emac_adapter *adpt);
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#endif /* _EMAC_H_ */
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