544 lines
17 KiB
C
544 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#include <linux/delay.h>
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#include <linux/of_address.h>
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#include "sun8i_dw_hdmi.h"
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/*
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* Address can be actually any value. Here is set to same value as
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* it is set in BSP driver.
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*/
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#define I2C_ADDR 0x69
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static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy,
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unsigned int clk_rate)
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{
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN);
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/* power down */
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dw_hdmi_phy_gen2_txpwron(hdmi, 0);
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dw_hdmi_phy_gen2_pddq(hdmi, 1);
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dw_hdmi_phy_reset(hdmi);
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dw_hdmi_phy_gen2_pddq(hdmi, 0);
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dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR);
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/*
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* Values are taken from BSP HDMI driver. Although AW didn't
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* release any documentation, explanation of this values can
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* be found in i.MX 6Dual/6Quad Reference Manual.
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*/
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if (clk_rate <= 27000000) {
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dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
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} else if (clk_rate <= 74250000) {
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dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09);
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} else if (clk_rate <= 148500000) {
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dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09);
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} else {
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06);
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dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10);
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dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e);
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dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09);
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}
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);
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dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17);
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dw_hdmi_phy_gen2_txpwron(hdmi, 1);
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return 0;
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}
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static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy,
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unsigned int clk_rate)
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{
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u32 pll_cfg1_init;
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u32 pll_cfg2_init;
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u32 ana_cfg1_end;
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u32 ana_cfg2_init;
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u32 ana_cfg3_init;
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u32 b_offset = 0;
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u32 val;
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/* bandwidth / frequency independent settings */
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pll_cfg1_init = SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN |
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SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN |
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SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(7) |
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SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(1) |
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SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN |
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SUN8I_HDMI_PHY_PLL_CFG1_CS |
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SUN8I_HDMI_PHY_PLL_CFG1_CP_S(2) |
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SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63) |
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SUN8I_HDMI_PHY_PLL_CFG1_BWS;
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pll_cfg2_init = SUN8I_HDMI_PHY_PLL_CFG2_SV_H |
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SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN |
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SUN8I_HDMI_PHY_PLL_CFG2_SDIV2;
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ana_cfg1_end = SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(1) |
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SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT |
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SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT |
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SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT |
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SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT |
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SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL |
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SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG |
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SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS |
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SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN |
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SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK |
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SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
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SUN8I_HDMI_PHY_ANA_CFG1_CKEN |
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SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
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SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
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SUN8I_HDMI_PHY_ANA_CFG1_ENBI;
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ana_cfg2_init = SUN8I_HDMI_PHY_ANA_CFG2_M_EN |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(1) |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(1);
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ana_cfg3_init = SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(0x3e0) |
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SUN8I_HDMI_PHY_ANA_CFG3_SDAEN |
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SUN8I_HDMI_PHY_ANA_CFG3_SCLEN;
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/* bandwidth / frequency dependent settings */
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if (clk_rate <= 27000000) {
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pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
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SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
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pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
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SUN8I_HDMI_PHY_PLL_CFG2_S(4);
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ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
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ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
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ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(3) |
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SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(5);
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} else if (clk_rate <= 74250000) {
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pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
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SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
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pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
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SUN8I_HDMI_PHY_PLL_CFG2_S(5);
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ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW;
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ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal);
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ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(5) |
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SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(7);
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} else if (clk_rate <= 148500000) {
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pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 |
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SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32);
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pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) |
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SUN8I_HDMI_PHY_PLL_CFG2_S(6);
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ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(2);
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ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(7) |
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SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(9);
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} else {
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b_offset = 2;
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pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63);
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pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(6) |
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SUN8I_HDMI_PHY_PLL_CFG2_S(7);
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ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
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SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);
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ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |
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SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13);
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}
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, pll_cfg1_init);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
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(u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
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pll_cfg2_init);
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usleep_range(10000, 15000);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG3_REG,
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SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
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SUN8I_HDMI_PHY_PLL_CFG1_PLLEN,
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SUN8I_HDMI_PHY_PLL_CFG1_PLLEN);
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msleep(100);
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/* get B value */
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regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
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val = (val & SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK) >>
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SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT;
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val = min(val + b_offset, (u32)0x3f);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
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SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
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SUN8I_HDMI_PHY_PLL_CFG1_REG_OD,
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SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 |
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SUN8I_HDMI_PHY_PLL_CFG1_REG_OD);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
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SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK,
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val << SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT);
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msleep(100);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, ana_cfg1_end);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG2_REG, ana_cfg2_init);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, ana_cfg3_init);
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return 0;
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}
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static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
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struct drm_display_mode *mode)
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{
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struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
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u32 val = 0;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC;
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val);
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if (phy->variant->has_phy_clk)
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clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000);
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return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000);
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};
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static void sun8i_hdmi_phy_disable_a83t(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy)
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{
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dw_hdmi_phy_gen2_txpwron(hdmi, 0);
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dw_hdmi_phy_gen2_pddq(hdmi, 1);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG,
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SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0);
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}
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static void sun8i_hdmi_phy_disable_h3(struct dw_hdmi *hdmi,
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struct sun8i_hdmi_phy *phy)
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{
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regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_LDOEN |
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SUN8I_HDMI_PHY_ANA_CFG1_ENVBS |
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SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
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regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0);
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}
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static void sun8i_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
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{
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struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data;
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phy->variant->phy_disable(hdmi, phy);
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}
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static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = {
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.init = &sun8i_hdmi_phy_config,
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.disable = &sun8i_hdmi_phy_disable,
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.read_hpd = &dw_hdmi_phy_read_hpd,
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.update_hpd = &dw_hdmi_phy_update_hpd,
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.setup_hpd = &dw_hdmi_phy_setup_hpd,
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};
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static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy)
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{
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK,
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SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK);
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/*
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* Set PHY I2C address. It must match to the address set by
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* dw_hdmi_phy_set_slave_addr().
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*/
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG,
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SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK,
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SUN8I_HDMI_PHY_DBG_CTRL_ADDR(I2C_ADDR));
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}
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static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy)
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{
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unsigned int val;
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regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_ENBI,
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SUN8I_HDMI_PHY_ANA_CFG1_ENBI);
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udelay(5);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN,
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SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_ENVBS,
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SUN8I_HDMI_PHY_ANA_CFG1_ENVBS);
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usleep_range(10, 20);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_LDOEN,
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SUN8I_HDMI_PHY_ANA_CFG1_LDOEN);
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udelay(5);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_CKEN,
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SUN8I_HDMI_PHY_ANA_CFG1_CKEN);
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usleep_range(40, 100);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL,
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SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL);
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usleep_range(100, 200);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG,
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SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2,
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 |
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2);
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/* wait for calibration to finish */
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regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val,
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(val & SUN8I_HDMI_PHY_ANA_STS_RCALEND2D),
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100, 2000);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK,
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SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK);
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regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
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SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK,
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 |
|
|
SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK);
|
|
|
|
/* enable DDC communication */
|
|
regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG,
|
|
SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
|
|
SUN8I_HDMI_PHY_ANA_CFG3_SDAEN,
|
|
SUN8I_HDMI_PHY_ANA_CFG3_SCLEN |
|
|
SUN8I_HDMI_PHY_ANA_CFG3_SDAEN);
|
|
|
|
/* set HW control of CEC pins */
|
|
regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0);
|
|
|
|
/* read calibration data */
|
|
regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val);
|
|
phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2;
|
|
}
|
|
|
|
void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy)
|
|
{
|
|
/* enable read access to HDMI controller */
|
|
regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG,
|
|
SUN8I_HDMI_PHY_READ_EN_MAGIC);
|
|
|
|
/* unscramble register offsets */
|
|
regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG,
|
|
SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC);
|
|
|
|
phy->variant->phy_init(phy);
|
|
}
|
|
|
|
const struct dw_hdmi_phy_ops *sun8i_hdmi_phy_get_ops(void)
|
|
{
|
|
return &sun8i_hdmi_phy_ops;
|
|
}
|
|
|
|
static struct regmap_config sun8i_hdmi_phy_regmap_config = {
|
|
.reg_bits = 32,
|
|
.val_bits = 32,
|
|
.reg_stride = 4,
|
|
.max_register = SUN8I_HDMI_PHY_CEC_REG,
|
|
.name = "phy"
|
|
};
|
|
|
|
static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = {
|
|
.phy_init = &sun8i_hdmi_phy_init_a83t,
|
|
.phy_disable = &sun8i_hdmi_phy_disable_a83t,
|
|
.phy_config = &sun8i_hdmi_phy_config_a83t,
|
|
};
|
|
|
|
static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = {
|
|
.has_phy_clk = true,
|
|
.phy_init = &sun8i_hdmi_phy_init_h3,
|
|
.phy_disable = &sun8i_hdmi_phy_disable_h3,
|
|
.phy_config = &sun8i_hdmi_phy_config_h3,
|
|
};
|
|
|
|
static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
|
|
{
|
|
.compatible = "allwinner,sun8i-a83t-hdmi-phy",
|
|
.data = &sun8i_a83t_hdmi_phy,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-h3-hdmi-phy",
|
|
.data = &sun8i_h3_hdmi_phy,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node)
|
|
{
|
|
const struct of_device_id *match;
|
|
struct device *dev = hdmi->dev;
|
|
struct sun8i_hdmi_phy *phy;
|
|
struct resource res;
|
|
void __iomem *regs;
|
|
int ret;
|
|
|
|
match = of_match_node(sun8i_hdmi_phy_of_table, node);
|
|
if (!match) {
|
|
dev_err(dev, "Incompatible HDMI PHY\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
|
|
if (!phy)
|
|
return -ENOMEM;
|
|
|
|
phy->variant = (struct sun8i_hdmi_phy_variant *)match->data;
|
|
|
|
ret = of_address_to_resource(node, 0, &res);
|
|
if (ret) {
|
|
dev_err(dev, "phy: Couldn't get our resources\n");
|
|
return ret;
|
|
}
|
|
|
|
regs = devm_ioremap_resource(dev, &res);
|
|
if (IS_ERR(regs)) {
|
|
dev_err(dev, "Couldn't map the HDMI PHY registers\n");
|
|
return PTR_ERR(regs);
|
|
}
|
|
|
|
phy->regs = devm_regmap_init_mmio(dev, regs,
|
|
&sun8i_hdmi_phy_regmap_config);
|
|
if (IS_ERR(phy->regs)) {
|
|
dev_err(dev, "Couldn't create the HDMI PHY regmap\n");
|
|
return PTR_ERR(phy->regs);
|
|
}
|
|
|
|
phy->clk_bus = of_clk_get_by_name(node, "bus");
|
|
if (IS_ERR(phy->clk_bus)) {
|
|
dev_err(dev, "Could not get bus clock\n");
|
|
return PTR_ERR(phy->clk_bus);
|
|
}
|
|
|
|
phy->clk_mod = of_clk_get_by_name(node, "mod");
|
|
if (IS_ERR(phy->clk_mod)) {
|
|
dev_err(dev, "Could not get mod clock\n");
|
|
ret = PTR_ERR(phy->clk_mod);
|
|
goto err_put_clk_bus;
|
|
}
|
|
|
|
if (phy->variant->has_phy_clk) {
|
|
phy->clk_pll0 = of_clk_get_by_name(node, "pll-0");
|
|
if (IS_ERR(phy->clk_pll0)) {
|
|
dev_err(dev, "Could not get pll-0 clock\n");
|
|
ret = PTR_ERR(phy->clk_pll0);
|
|
goto err_put_clk_mod;
|
|
}
|
|
|
|
ret = sun8i_phy_clk_create(phy, dev);
|
|
if (ret) {
|
|
dev_err(dev, "Couldn't create the PHY clock\n");
|
|
goto err_put_clk_pll0;
|
|
}
|
|
}
|
|
|
|
phy->rst_phy = of_reset_control_get_shared(node, "phy");
|
|
if (IS_ERR(phy->rst_phy)) {
|
|
dev_err(dev, "Could not get phy reset control\n");
|
|
ret = PTR_ERR(phy->rst_phy);
|
|
goto err_put_clk_pll0;
|
|
}
|
|
|
|
ret = reset_control_deassert(phy->rst_phy);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot deassert phy reset control: %d\n", ret);
|
|
goto err_put_rst_phy;
|
|
}
|
|
|
|
ret = clk_prepare_enable(phy->clk_bus);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot enable bus clock: %d\n", ret);
|
|
goto err_deassert_rst_phy;
|
|
}
|
|
|
|
ret = clk_prepare_enable(phy->clk_mod);
|
|
if (ret) {
|
|
dev_err(dev, "Cannot enable mod clock: %d\n", ret);
|
|
goto err_disable_clk_bus;
|
|
}
|
|
|
|
hdmi->phy = phy;
|
|
|
|
return 0;
|
|
|
|
err_disable_clk_bus:
|
|
clk_disable_unprepare(phy->clk_bus);
|
|
err_deassert_rst_phy:
|
|
reset_control_assert(phy->rst_phy);
|
|
err_put_rst_phy:
|
|
reset_control_put(phy->rst_phy);
|
|
err_put_clk_pll0:
|
|
if (phy->variant->has_phy_clk)
|
|
clk_put(phy->clk_pll0);
|
|
err_put_clk_mod:
|
|
clk_put(phy->clk_mod);
|
|
err_put_clk_bus:
|
|
clk_put(phy->clk_bus);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi)
|
|
{
|
|
struct sun8i_hdmi_phy *phy = hdmi->phy;
|
|
|
|
clk_disable_unprepare(phy->clk_mod);
|
|
clk_disable_unprepare(phy->clk_bus);
|
|
|
|
reset_control_assert(phy->rst_phy);
|
|
|
|
reset_control_put(phy->rst_phy);
|
|
|
|
if (phy->variant->has_phy_clk)
|
|
clk_put(phy->clk_pll0);
|
|
clk_put(phy->clk_mod);
|
|
clk_put(phy->clk_bus);
|
|
}
|