588 lines
16 KiB
C
588 lines
16 KiB
C
/*
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* arch/arm/include/asm/tlbflush.h
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*
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* Copyright (C) 1999-2003 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASMARM_TLBFLUSH_H
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#define _ASMARM_TLBFLUSH_H
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#ifdef CONFIG_MMU
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#include <asm/glue.h>
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#define TLB_V3_PAGE (1 << 0)
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#define TLB_V4_U_PAGE (1 << 1)
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#define TLB_V4_D_PAGE (1 << 2)
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#define TLB_V4_I_PAGE (1 << 3)
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#define TLB_V6_U_PAGE (1 << 4)
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#define TLB_V6_D_PAGE (1 << 5)
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#define TLB_V6_I_PAGE (1 << 6)
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#define TLB_V3_FULL (1 << 8)
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#define TLB_V4_U_FULL (1 << 9)
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#define TLB_V4_D_FULL (1 << 10)
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#define TLB_V4_I_FULL (1 << 11)
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#define TLB_V6_U_FULL (1 << 12)
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#define TLB_V6_D_FULL (1 << 13)
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#define TLB_V6_I_FULL (1 << 14)
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#define TLB_V6_U_ASID (1 << 16)
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#define TLB_V6_D_ASID (1 << 17)
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#define TLB_V6_I_ASID (1 << 18)
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#define TLB_BTB (1 << 28)
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/* Unified Inner Shareable TLB operations (ARMv7 MP extensions) */
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#define TLB_V7_UIS_PAGE (1 << 19)
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#define TLB_V7_UIS_FULL (1 << 20)
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#define TLB_V7_UIS_ASID (1 << 21)
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/* Inner Shareable BTB operation (ARMv7 MP extensions) */
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#define TLB_V7_IS_BTB (1 << 22)
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#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
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#define TLB_DCLEAN (1 << 30)
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#define TLB_WB (1 << 31)
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/*
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* MMU TLB Model
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* =============
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*
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* We have the following to choose from:
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* v3 - ARMv3
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* v4 - ARMv4 without write buffer
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* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
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* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
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* fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
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* fa - Faraday (v4 with write buffer with UTLB and branch target buffer (BTB))
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* v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
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* v7wbi - identical to v6wbi
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*/
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#undef _TLB
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#undef MULTI_TLB
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#ifdef CONFIG_SMP_ON_UP
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#define MULTI_TLB 1
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#endif
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#define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE)
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#ifdef CONFIG_CPU_TLB_V3
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# define v3_possible_flags v3_tlb_flags
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# define v3_always_flags v3_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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# define _TLB v3
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# endif
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#else
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# define v3_possible_flags 0
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# define v3_always_flags (-1UL)
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#endif
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#define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE)
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#ifdef CONFIG_CPU_TLB_V4WT
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# define v4_possible_flags v4_tlb_flags
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# define v4_always_flags v4_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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# define _TLB v4
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# endif
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#else
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# define v4_possible_flags 0
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# define v4_always_flags (-1UL)
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#endif
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#define fa_tlb_flags (TLB_WB | TLB_BTB | TLB_DCLEAN | \
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TLB_V4_U_FULL | TLB_V4_U_PAGE)
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#ifdef CONFIG_CPU_TLB_FA
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# define fa_possible_flags fa_tlb_flags
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# define fa_always_flags fa_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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# define _TLB fa
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# endif
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#else
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# define fa_possible_flags 0
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# define fa_always_flags (-1UL)
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#endif
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#define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
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TLB_V4_I_FULL | TLB_V4_D_FULL | \
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TLB_V4_I_PAGE | TLB_V4_D_PAGE)
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#ifdef CONFIG_CPU_TLB_V4WBI
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# define v4wbi_possible_flags v4wbi_tlb_flags
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# define v4wbi_always_flags v4wbi_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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# define _TLB v4wbi
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# endif
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#else
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# define v4wbi_possible_flags 0
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# define v4wbi_always_flags (-1UL)
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#endif
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#define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
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TLB_V4_I_FULL | TLB_V4_D_FULL | \
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TLB_V4_I_PAGE | TLB_V4_D_PAGE)
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#ifdef CONFIG_CPU_TLB_FEROCEON
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# define fr_possible_flags fr_tlb_flags
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# define fr_always_flags fr_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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# define _TLB v4wbi
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# endif
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#else
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# define fr_possible_flags 0
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# define fr_always_flags (-1UL)
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#endif
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#define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \
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TLB_V4_I_FULL | TLB_V4_D_FULL | \
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TLB_V4_D_PAGE)
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#ifdef CONFIG_CPU_TLB_V4WB
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# define v4wb_possible_flags v4wb_tlb_flags
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# define v4wb_always_flags v4wb_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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# define _TLB v4wb
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# endif
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#else
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# define v4wb_possible_flags 0
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# define v4wb_always_flags (-1UL)
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#endif
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#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
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TLB_V6_I_FULL | TLB_V6_D_FULL | \
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TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
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TLB_V6_I_ASID | TLB_V6_D_ASID)
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#ifdef CONFIG_CPU_TLB_V6
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# define v6wbi_possible_flags v6wbi_tlb_flags
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# define v6wbi_always_flags v6wbi_tlb_flags
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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# define _TLB v6wbi
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# endif
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#else
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# define v6wbi_possible_flags 0
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# define v6wbi_always_flags (-1UL)
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#endif
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#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
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TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
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#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \
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TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
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#ifdef CONFIG_CPU_TLB_V7
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# ifdef CONFIG_SMP_ON_UP
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# define v7wbi_possible_flags (v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
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# define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
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# elif defined(CONFIG_SMP)
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# define v7wbi_possible_flags v7wbi_tlb_flags_smp
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# define v7wbi_always_flags v7wbi_tlb_flags_smp
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# else
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# define v7wbi_possible_flags v7wbi_tlb_flags_up
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# define v7wbi_always_flags v7wbi_tlb_flags_up
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# endif
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# ifdef _TLB
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# define MULTI_TLB 1
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# else
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# define _TLB v7wbi
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# endif
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#else
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# define v7wbi_possible_flags 0
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# define v7wbi_always_flags (-1UL)
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#endif
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#ifndef _TLB
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#error Unknown TLB model
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#endif
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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struct cpu_tlb_fns {
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void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
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void (*flush_kern_range)(unsigned long, unsigned long);
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unsigned long tlb_flags;
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};
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/*
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* Select the calling method
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*/
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#ifdef MULTI_TLB
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#define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
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#define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
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#else
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#define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
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#define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
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extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
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extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
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#endif
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extern struct cpu_tlb_fns cpu_tlb;
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#define __cpu_tlb_flags cpu_tlb.tlb_flags
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/*
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* TLB Management
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* ==============
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*
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* The arch/arm/mm/tlb-*.S files implement these methods.
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*
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* The TLB specific code is expected to perform whatever tests it
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* needs to determine if it should invalidate the TLB for each
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* call. Start addresses are inclusive and end addresses are
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* exclusive; it is safe to round these addresses down.
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*
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* flush_tlb_all()
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*
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* Invalidate the entire TLB.
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*
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* flush_tlb_mm(mm)
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*
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* Invalidate all TLB entries in a particular address
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* space.
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* - mm - mm_struct describing address space
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*
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* flush_tlb_range(mm,start,end)
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*
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* Invalidate a range of TLB entries in the specified
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* address space.
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* - mm - mm_struct describing address space
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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*
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* flush_tlb_page(vaddr,vma)
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*
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* Invalidate the specified page in the specified address range.
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* - vaddr - virtual address (may not be aligned)
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* - vma - vma_struct describing address range
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*
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* flush_kern_tlb_page(kaddr)
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*
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* Invalidate the TLB entry for the specified page. The address
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* will be in the kernels virtual memory space. Current uses
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* only require the D-TLB to be invalidated.
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* - kaddr - Kernel virtual memory address
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*/
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/*
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* We optimise the code below by:
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* - building a set of TLB flags that might be set in __cpu_tlb_flags
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* - building a set of TLB flags that will always be set in __cpu_tlb_flags
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* - if we're going to need __cpu_tlb_flags, access it once and only once
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*
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* This allows us to build optimal assembly for the single-CPU type case,
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* and as close to optimal given the compiler constrants for multi-CPU
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* case. We could do better for the multi-CPU case if the compiler
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* implemented the "%?" method, but this has been discontinued due to too
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* many people getting it wrong.
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*/
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#define possible_tlb_flags (v3_possible_flags | \
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v4_possible_flags | \
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v4wbi_possible_flags | \
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fr_possible_flags | \
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v4wb_possible_flags | \
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fa_possible_flags | \
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v6wbi_possible_flags | \
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v7wbi_possible_flags)
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#define always_tlb_flags (v3_always_flags & \
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v4_always_flags & \
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v4wbi_always_flags & \
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fr_always_flags & \
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v4wb_always_flags & \
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fa_always_flags & \
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v6wbi_always_flags & \
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v7wbi_always_flags)
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#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
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static inline void local_flush_tlb_all(void)
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{
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const int zero = 0;
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const unsigned int __tlb_flag = __cpu_tlb_flags;
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if (tlb_flag(TLB_WB))
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dsb();
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if (tlb_flag(TLB_V3_FULL))
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asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
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asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
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asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V7_UIS_FULL))
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asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
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dsb();
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isb();
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}
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if (tlb_flag(TLB_V7_IS_BTB)) {
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/* flush the branch target cache */
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asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
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dsb();
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isb();
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}
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}
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static inline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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const int zero = 0;
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const int asid = ASID(mm);
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const unsigned int __tlb_flag = __cpu_tlb_flags;
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if (tlb_flag(TLB_WB))
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dsb();
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if (cpumask_test_cpu(get_cpu(), mm_cpumask(mm))) {
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if (tlb_flag(TLB_V3_FULL))
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asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_U_FULL))
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asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_D_FULL))
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asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V4_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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}
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put_cpu();
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if (tlb_flag(TLB_V6_U_ASID))
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asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_V6_D_ASID))
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asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_V6_I_ASID))
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asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
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if (tlb_flag(TLB_V7_UIS_ASID))
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#ifdef CONFIG_ARM_ERRATA_720789
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asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
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#else
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asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
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#endif
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
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dsb();
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}
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if (tlb_flag(TLB_V7_IS_BTB)) {
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/* flush the branch target cache */
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asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
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dsb();
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isb();
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}
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}
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static inline void
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local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
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{
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const int zero = 0;
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const unsigned int __tlb_flag = __cpu_tlb_flags;
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uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
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if (tlb_flag(TLB_WB))
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dsb();
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if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
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if (tlb_flag(TLB_V3_PAGE))
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asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V4_U_PAGE))
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asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V4_D_PAGE))
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V4_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
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if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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}
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if (tlb_flag(TLB_V6_U_PAGE))
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asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V6_D_PAGE))
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V6_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
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if (tlb_flag(TLB_V7_UIS_PAGE))
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#ifdef CONFIG_ARM_ERRATA_720789
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asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc");
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#else
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asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
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#endif
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
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dsb();
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}
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if (tlb_flag(TLB_V7_IS_BTB)) {
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/* flush the branch target cache */
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asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
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dsb();
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isb();
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}
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}
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static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
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{
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const int zero = 0;
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const unsigned int __tlb_flag = __cpu_tlb_flags;
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kaddr &= PAGE_MASK;
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if (tlb_flag(TLB_WB))
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dsb();
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if (tlb_flag(TLB_V3_PAGE))
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asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V4_U_PAGE))
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asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V4_D_PAGE))
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V4_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
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if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
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asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
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if (tlb_flag(TLB_V6_U_PAGE))
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asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V6_D_PAGE))
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asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V6_I_PAGE))
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asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_V7_UIS_PAGE))
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asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (kaddr) : "cc");
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if (tlb_flag(TLB_BTB)) {
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/* flush the branch target cache */
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asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
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dsb();
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isb();
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}
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if (tlb_flag(TLB_V7_IS_BTB)) {
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/* flush the branch target cache */
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asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero) : "cc");
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dsb();
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isb();
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}
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}
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/*
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* flush_pmd_entry
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*
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* Flush a PMD entry (word aligned, or double-word aligned) to
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* RAM if the TLB for the CPU we are running on requires this.
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* This is typically used when we are creating PMD entries.
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*
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* clean_pmd_entry
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*
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* Clean (but don't drain the write buffer) if the CPU requires
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* these operations. This is typically used when we are removing
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* PMD entries.
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*/
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static inline void flush_pmd_entry(pmd_t *pmd)
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{
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const unsigned int __tlb_flag = __cpu_tlb_flags;
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if (tlb_flag(TLB_DCLEAN))
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asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
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: : "r" (pmd) : "cc");
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if (tlb_flag(TLB_L2CLEAN_FR))
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asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
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: : "r" (pmd) : "cc");
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if (tlb_flag(TLB_WB))
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dsb();
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}
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static inline void clean_pmd_entry(pmd_t *pmd)
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{
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const unsigned int __tlb_flag = __cpu_tlb_flags;
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if (tlb_flag(TLB_DCLEAN))
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asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
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: : "r" (pmd) : "cc");
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if (tlb_flag(TLB_L2CLEAN_FR))
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asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
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: : "r" (pmd) : "cc");
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}
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#undef tlb_flag
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#undef always_tlb_flags
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#undef possible_tlb_flags
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/*
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* Convert calls to our calling convention.
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*/
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#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
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#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
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#ifndef CONFIG_SMP
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#define flush_tlb_all local_flush_tlb_all
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#define flush_tlb_mm local_flush_tlb_mm
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#define flush_tlb_page local_flush_tlb_page
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#define flush_tlb_kernel_page local_flush_tlb_kernel_page
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#define flush_tlb_range local_flush_tlb_range
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#define flush_tlb_kernel_range local_flush_tlb_kernel_range
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#else
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extern void flush_tlb_all(void);
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extern void flush_tlb_mm(struct mm_struct *mm);
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extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
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extern void flush_tlb_kernel_page(unsigned long kaddr);
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extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
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extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
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#endif
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/*
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* If PG_dcache_clean is not set for the page, we need to ensure that any
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* cache entries for the kernels virtual memory range are written
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* back to the page. On ARMv6 and later, the cache coherency is handled via
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* the set_pte_at() function.
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*/
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#if __LINUX_ARM_ARCH__ < 6
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extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
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pte_t *ptep);
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#else
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long addr, pte_t *ptep)
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{
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}
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#endif
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#endif
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#endif /* CONFIG_MMU */
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#endif
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