668 lines
17 KiB
C
668 lines
17 KiB
C
/*
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* Copyright (C) 2014 Free Electrons
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* Copyright (C) 2014 Atmel
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*
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include "atmel_hlcdc_dc.h"
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static void
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atmel_hlcdc_layer_fb_flip_release(struct drm_flip_work *work, void *val)
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{
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struct atmel_hlcdc_layer_fb_flip *flip = val;
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if (flip->fb)
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drm_framebuffer_unreference(flip->fb);
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kfree(flip);
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}
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static void
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atmel_hlcdc_layer_fb_flip_destroy(struct atmel_hlcdc_layer_fb_flip *flip)
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{
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if (flip->fb)
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drm_framebuffer_unreference(flip->fb);
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kfree(flip->task);
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kfree(flip);
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}
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static void
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atmel_hlcdc_layer_fb_flip_release_queue(struct atmel_hlcdc_layer *layer,
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struct atmel_hlcdc_layer_fb_flip *flip)
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{
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int i;
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if (!flip)
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return;
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for (i = 0; i < layer->max_planes; i++) {
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if (!flip->dscrs[i])
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break;
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flip->dscrs[i]->status = 0;
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flip->dscrs[i] = NULL;
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}
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drm_flip_work_queue_task(&layer->gc, flip->task);
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drm_flip_work_commit(&layer->gc, layer->wq);
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}
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static void atmel_hlcdc_layer_update_reset(struct atmel_hlcdc_layer *layer,
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int id)
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{
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struct atmel_hlcdc_layer_update *upd = &layer->update;
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struct atmel_hlcdc_layer_update_slot *slot;
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if (id < 0 || id > 1)
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return;
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slot = &upd->slots[id];
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bitmap_clear(slot->updated_configs, 0, layer->desc->nconfigs);
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memset(slot->configs, 0,
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sizeof(*slot->configs) * layer->desc->nconfigs);
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if (slot->fb_flip) {
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atmel_hlcdc_layer_fb_flip_release_queue(layer, slot->fb_flip);
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slot->fb_flip = NULL;
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}
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}
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static void atmel_hlcdc_layer_update_apply(struct atmel_hlcdc_layer *layer)
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{
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struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
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const struct atmel_hlcdc_layer_desc *desc = layer->desc;
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struct atmel_hlcdc_layer_update *upd = &layer->update;
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struct regmap *regmap = layer->hlcdc->regmap;
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struct atmel_hlcdc_layer_update_slot *slot;
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struct atmel_hlcdc_layer_fb_flip *fb_flip;
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struct atmel_hlcdc_dma_channel_dscr *dscr;
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unsigned int cfg;
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u32 action = 0;
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int i = 0;
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if (upd->pending < 0 || upd->pending > 1)
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return;
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slot = &upd->slots[upd->pending];
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for_each_set_bit(cfg, slot->updated_configs, layer->desc->nconfigs) {
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regmap_write(regmap,
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desc->regs_offset +
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ATMEL_HLCDC_LAYER_CFG(layer, cfg),
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slot->configs[cfg]);
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action |= ATMEL_HLCDC_LAYER_UPDATE;
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}
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fb_flip = slot->fb_flip;
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if (!fb_flip->fb)
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goto apply;
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if (dma->status == ATMEL_HLCDC_LAYER_DISABLED) {
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for (i = 0; i < fb_flip->ngems; i++) {
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dscr = fb_flip->dscrs[i];
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dscr->ctrl = ATMEL_HLCDC_LAYER_DFETCH |
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ATMEL_HLCDC_LAYER_DMA_IRQ |
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ATMEL_HLCDC_LAYER_ADD_IRQ |
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ATMEL_HLCDC_LAYER_DONE_IRQ;
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regmap_write(regmap,
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desc->regs_offset +
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ATMEL_HLCDC_LAYER_PLANE_ADDR(i),
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dscr->addr);
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regmap_write(regmap,
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desc->regs_offset +
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ATMEL_HLCDC_LAYER_PLANE_CTRL(i),
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dscr->ctrl);
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regmap_write(regmap,
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desc->regs_offset +
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ATMEL_HLCDC_LAYER_PLANE_NEXT(i),
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dscr->next);
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}
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action |= ATMEL_HLCDC_LAYER_DMA_CHAN;
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dma->status = ATMEL_HLCDC_LAYER_ENABLED;
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} else {
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for (i = 0; i < fb_flip->ngems; i++) {
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dscr = fb_flip->dscrs[i];
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dscr->ctrl = ATMEL_HLCDC_LAYER_DFETCH |
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ATMEL_HLCDC_LAYER_DMA_IRQ |
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ATMEL_HLCDC_LAYER_DSCR_IRQ |
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ATMEL_HLCDC_LAYER_DONE_IRQ;
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regmap_write(regmap,
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desc->regs_offset +
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ATMEL_HLCDC_LAYER_PLANE_HEAD(i),
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dscr->next);
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}
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action |= ATMEL_HLCDC_LAYER_A2Q;
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}
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/* Release unneeded descriptors */
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for (i = fb_flip->ngems; i < layer->max_planes; i++) {
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fb_flip->dscrs[i]->status = 0;
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fb_flip->dscrs[i] = NULL;
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}
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dma->queue = fb_flip;
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slot->fb_flip = NULL;
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apply:
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if (action)
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regmap_write(regmap,
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desc->regs_offset + ATMEL_HLCDC_LAYER_CHER,
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action);
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atmel_hlcdc_layer_update_reset(layer, upd->pending);
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upd->pending = -1;
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}
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void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer)
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{
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struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
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const struct atmel_hlcdc_layer_desc *desc = layer->desc;
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struct regmap *regmap = layer->hlcdc->regmap;
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struct atmel_hlcdc_layer_fb_flip *flip;
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unsigned long flags;
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unsigned int isr, imr;
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unsigned int status;
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unsigned int plane_status;
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u32 flip_status;
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int i;
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regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_IMR, &imr);
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regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR, &isr);
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status = imr & isr;
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if (!status)
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return;
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spin_lock_irqsave(&layer->lock, flags);
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flip = dma->queue ? dma->queue : dma->cur;
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if (!flip) {
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spin_unlock_irqrestore(&layer->lock, flags);
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return;
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}
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/*
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* Set LOADED and DONE flags: they'll be cleared if at least one
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* memory plane is not LOADED or DONE.
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*/
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flip_status = ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED |
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ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE;
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for (i = 0; i < flip->ngems; i++) {
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plane_status = (status >> (8 * i));
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if (plane_status &
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(ATMEL_HLCDC_LAYER_ADD_IRQ |
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ATMEL_HLCDC_LAYER_DSCR_IRQ) &
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~flip->dscrs[i]->ctrl) {
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flip->dscrs[i]->status |=
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ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED;
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flip->dscrs[i]->ctrl |=
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ATMEL_HLCDC_LAYER_ADD_IRQ |
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ATMEL_HLCDC_LAYER_DSCR_IRQ;
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}
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if (plane_status &
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ATMEL_HLCDC_LAYER_DONE_IRQ &
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~flip->dscrs[i]->ctrl) {
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flip->dscrs[i]->status |=
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ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE;
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flip->dscrs[i]->ctrl |=
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ATMEL_HLCDC_LAYER_DONE_IRQ;
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}
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if (plane_status & ATMEL_HLCDC_LAYER_OVR_IRQ)
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flip->dscrs[i]->status |=
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ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN;
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/*
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* Clear LOADED and DONE flags if the memory plane is either
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* not LOADED or not DONE.
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*/
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if (!(flip->dscrs[i]->status &
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ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED))
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flip_status &= ~ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED;
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if (!(flip->dscrs[i]->status &
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ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE))
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flip_status &= ~ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE;
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/*
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* An overrun on one memory plane impact the whole framebuffer
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* transfer, hence we set the OVERRUN flag as soon as there's
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* one memory plane reporting such an overrun.
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*/
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flip_status |= flip->dscrs[i]->status &
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ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN;
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}
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/* Get changed bits */
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flip_status ^= flip->status;
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flip->status |= flip_status;
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if (flip_status & ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED) {
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atmel_hlcdc_layer_fb_flip_release_queue(layer, dma->cur);
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dma->cur = dma->queue;
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dma->queue = NULL;
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}
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if (flip_status & ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE) {
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atmel_hlcdc_layer_fb_flip_release_queue(layer, dma->cur);
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dma->cur = NULL;
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}
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if (flip_status & ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN) {
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regmap_write(regmap,
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desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR,
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ATMEL_HLCDC_LAYER_RST);
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if (dma->queue)
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atmel_hlcdc_layer_fb_flip_release_queue(layer,
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dma->queue);
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if (dma->cur)
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atmel_hlcdc_layer_fb_flip_release_queue(layer,
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dma->cur);
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dma->cur = NULL;
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dma->queue = NULL;
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}
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if (!dma->queue) {
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atmel_hlcdc_layer_update_apply(layer);
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if (!dma->cur)
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dma->status = ATMEL_HLCDC_LAYER_DISABLED;
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}
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spin_unlock_irqrestore(&layer->lock, flags);
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}
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int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer)
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{
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struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
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struct atmel_hlcdc_layer_update *upd = &layer->update;
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struct regmap *regmap = layer->hlcdc->regmap;
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const struct atmel_hlcdc_layer_desc *desc = layer->desc;
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unsigned long flags;
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unsigned int isr;
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spin_lock_irqsave(&layer->lock, flags);
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/* Disable the layer */
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regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR,
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ATMEL_HLCDC_LAYER_RST);
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/* Clear all pending interrupts */
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regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR, &isr);
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/* Discard current and queued framebuffer transfers. */
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if (dma->cur) {
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atmel_hlcdc_layer_fb_flip_release_queue(layer, dma->cur);
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dma->cur = NULL;
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}
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if (dma->queue) {
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atmel_hlcdc_layer_fb_flip_release_queue(layer, dma->queue);
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dma->queue = NULL;
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}
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/*
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* Then discard the pending update request (if any) to prevent
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* DMA irq handler from restarting the DMA channel after it has
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* been disabled.
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*/
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if (upd->pending >= 0) {
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atmel_hlcdc_layer_update_reset(layer, upd->pending);
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upd->pending = -1;
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}
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dma->status = ATMEL_HLCDC_LAYER_DISABLED;
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spin_unlock_irqrestore(&layer->lock, flags);
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return 0;
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}
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int atmel_hlcdc_layer_update_start(struct atmel_hlcdc_layer *layer)
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{
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struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
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struct atmel_hlcdc_layer_update *upd = &layer->update;
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struct regmap *regmap = layer->hlcdc->regmap;
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struct atmel_hlcdc_layer_fb_flip *fb_flip;
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struct atmel_hlcdc_layer_update_slot *slot;
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unsigned long flags;
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int i, j = 0;
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fb_flip = kzalloc(sizeof(*fb_flip), GFP_KERNEL);
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if (!fb_flip)
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return -ENOMEM;
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fb_flip->task = drm_flip_work_allocate_task(fb_flip, GFP_KERNEL);
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if (!fb_flip->task) {
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kfree(fb_flip);
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return -ENOMEM;
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}
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spin_lock_irqsave(&layer->lock, flags);
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upd->next = upd->pending ? 0 : 1;
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slot = &upd->slots[upd->next];
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for (i = 0; i < layer->max_planes * 4; i++) {
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if (!dma->dscrs[i].status) {
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fb_flip->dscrs[j++] = &dma->dscrs[i];
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dma->dscrs[i].status =
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ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED;
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if (j == layer->max_planes)
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break;
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}
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}
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if (j < layer->max_planes) {
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for (i = 0; i < j; i++)
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fb_flip->dscrs[i]->status = 0;
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}
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if (j < layer->max_planes) {
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spin_unlock_irqrestore(&layer->lock, flags);
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atmel_hlcdc_layer_fb_flip_destroy(fb_flip);
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return -EBUSY;
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}
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slot->fb_flip = fb_flip;
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if (upd->pending >= 0) {
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memcpy(slot->configs,
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upd->slots[upd->pending].configs,
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layer->desc->nconfigs * sizeof(u32));
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memcpy(slot->updated_configs,
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upd->slots[upd->pending].updated_configs,
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DIV_ROUND_UP(layer->desc->nconfigs,
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BITS_PER_BYTE * sizeof(unsigned long)) *
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sizeof(unsigned long));
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slot->fb_flip->fb = upd->slots[upd->pending].fb_flip->fb;
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if (upd->slots[upd->pending].fb_flip->fb) {
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slot->fb_flip->fb =
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upd->slots[upd->pending].fb_flip->fb;
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slot->fb_flip->ngems =
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upd->slots[upd->pending].fb_flip->ngems;
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drm_framebuffer_reference(slot->fb_flip->fb);
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}
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} else {
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regmap_bulk_read(regmap,
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layer->desc->regs_offset +
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ATMEL_HLCDC_LAYER_CFG(layer, 0),
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upd->slots[upd->next].configs,
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layer->desc->nconfigs);
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}
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spin_unlock_irqrestore(&layer->lock, flags);
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return 0;
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}
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void atmel_hlcdc_layer_update_rollback(struct atmel_hlcdc_layer *layer)
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{
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struct atmel_hlcdc_layer_update *upd = &layer->update;
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atmel_hlcdc_layer_update_reset(layer, upd->next);
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upd->next = -1;
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}
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void atmel_hlcdc_layer_update_set_fb(struct atmel_hlcdc_layer *layer,
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struct drm_framebuffer *fb,
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unsigned int *offsets)
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{
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struct atmel_hlcdc_layer_update *upd = &layer->update;
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struct atmel_hlcdc_layer_fb_flip *fb_flip;
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struct atmel_hlcdc_layer_update_slot *slot;
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struct atmel_hlcdc_dma_channel_dscr *dscr;
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struct drm_framebuffer *old_fb;
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int nplanes = 0;
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int i;
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if (upd->next < 0 || upd->next > 1)
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return;
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if (fb)
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nplanes = drm_format_num_planes(fb->pixel_format);
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if (nplanes > layer->max_planes)
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return;
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slot = &upd->slots[upd->next];
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fb_flip = slot->fb_flip;
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old_fb = slot->fb_flip->fb;
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for (i = 0; i < nplanes; i++) {
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struct drm_gem_cma_object *gem;
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dscr = slot->fb_flip->dscrs[i];
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gem = drm_fb_cma_get_gem_obj(fb, i);
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dscr->addr = gem->paddr + offsets[i];
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}
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fb_flip->ngems = nplanes;
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fb_flip->fb = fb;
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if (fb)
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drm_framebuffer_reference(fb);
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if (old_fb)
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drm_framebuffer_unreference(old_fb);
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}
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void atmel_hlcdc_layer_update_cfg(struct atmel_hlcdc_layer *layer, int cfg,
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u32 mask, u32 val)
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{
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struct atmel_hlcdc_layer_update *upd = &layer->update;
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struct atmel_hlcdc_layer_update_slot *slot;
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if (upd->next < 0 || upd->next > 1)
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return;
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if (cfg >= layer->desc->nconfigs)
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return;
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slot = &upd->slots[upd->next];
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slot->configs[cfg] &= ~mask;
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slot->configs[cfg] |= (val & mask);
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set_bit(cfg, slot->updated_configs);
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}
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void atmel_hlcdc_layer_update_commit(struct atmel_hlcdc_layer *layer)
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{
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struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
|
|
struct atmel_hlcdc_layer_update *upd = &layer->update;
|
|
struct atmel_hlcdc_layer_update_slot *slot;
|
|
unsigned long flags;
|
|
|
|
if (upd->next < 0 || upd->next > 1)
|
|
return;
|
|
|
|
slot = &upd->slots[upd->next];
|
|
|
|
spin_lock_irqsave(&layer->lock, flags);
|
|
|
|
/*
|
|
* Release pending update request and replace it by the new one.
|
|
*/
|
|
if (upd->pending >= 0)
|
|
atmel_hlcdc_layer_update_reset(layer, upd->pending);
|
|
|
|
upd->pending = upd->next;
|
|
upd->next = -1;
|
|
|
|
if (!dma->queue)
|
|
atmel_hlcdc_layer_update_apply(layer);
|
|
|
|
spin_unlock_irqrestore(&layer->lock, flags);
|
|
|
|
|
|
upd->next = -1;
|
|
}
|
|
|
|
static int atmel_hlcdc_layer_dma_init(struct drm_device *dev,
|
|
struct atmel_hlcdc_layer *layer)
|
|
{
|
|
struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
|
|
dma_addr_t dma_addr;
|
|
int i;
|
|
|
|
dma->dscrs = dma_alloc_coherent(dev->dev,
|
|
layer->max_planes * 4 *
|
|
sizeof(*dma->dscrs),
|
|
&dma_addr, GFP_KERNEL);
|
|
if (!dma->dscrs)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < layer->max_planes * 4; i++) {
|
|
struct atmel_hlcdc_dma_channel_dscr *dscr = &dma->dscrs[i];
|
|
|
|
dscr->next = dma_addr + (i * sizeof(*dscr));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void atmel_hlcdc_layer_dma_cleanup(struct drm_device *dev,
|
|
struct atmel_hlcdc_layer *layer)
|
|
{
|
|
struct atmel_hlcdc_layer_dma_channel *dma = &layer->dma;
|
|
int i;
|
|
|
|
for (i = 0; i < layer->max_planes * 4; i++) {
|
|
struct atmel_hlcdc_dma_channel_dscr *dscr = &dma->dscrs[i];
|
|
|
|
dscr->status = 0;
|
|
}
|
|
|
|
dma_free_coherent(dev->dev, layer->max_planes * 4 *
|
|
sizeof(*dma->dscrs), dma->dscrs,
|
|
dma->dscrs[0].next);
|
|
}
|
|
|
|
static int atmel_hlcdc_layer_update_init(struct drm_device *dev,
|
|
struct atmel_hlcdc_layer *layer,
|
|
const struct atmel_hlcdc_layer_desc *desc)
|
|
{
|
|
struct atmel_hlcdc_layer_update *upd = &layer->update;
|
|
int updated_size;
|
|
void *buffer;
|
|
int i;
|
|
|
|
updated_size = DIV_ROUND_UP(desc->nconfigs,
|
|
BITS_PER_BYTE *
|
|
sizeof(unsigned long));
|
|
|
|
buffer = devm_kzalloc(dev->dev,
|
|
((desc->nconfigs * sizeof(u32)) +
|
|
(updated_size * sizeof(unsigned long))) * 2,
|
|
GFP_KERNEL);
|
|
if (!buffer)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
upd->slots[i].updated_configs = buffer;
|
|
buffer += updated_size * sizeof(unsigned long);
|
|
upd->slots[i].configs = buffer;
|
|
buffer += desc->nconfigs * sizeof(u32);
|
|
}
|
|
|
|
upd->pending = -1;
|
|
upd->next = -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int atmel_hlcdc_layer_init(struct drm_device *dev,
|
|
struct atmel_hlcdc_layer *layer,
|
|
const struct atmel_hlcdc_layer_desc *desc)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = dev->dev_private;
|
|
struct regmap *regmap = dc->hlcdc->regmap;
|
|
unsigned int tmp;
|
|
int ret;
|
|
int i;
|
|
|
|
layer->hlcdc = dc->hlcdc;
|
|
layer->wq = dc->wq;
|
|
layer->desc = desc;
|
|
|
|
regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR,
|
|
ATMEL_HLCDC_LAYER_RST);
|
|
for (i = 0; i < desc->formats->nformats; i++) {
|
|
int nplanes = drm_format_num_planes(desc->formats->formats[i]);
|
|
|
|
if (nplanes > layer->max_planes)
|
|
layer->max_planes = nplanes;
|
|
}
|
|
|
|
spin_lock_init(&layer->lock);
|
|
drm_flip_work_init(&layer->gc, desc->name,
|
|
atmel_hlcdc_layer_fb_flip_release);
|
|
ret = atmel_hlcdc_layer_dma_init(dev, layer);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = atmel_hlcdc_layer_update_init(dev, layer, desc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Flush Status Register */
|
|
regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_IDR,
|
|
0xffffffff);
|
|
regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR,
|
|
&tmp);
|
|
|
|
tmp = 0;
|
|
for (i = 0; i < layer->max_planes; i++)
|
|
tmp |= (ATMEL_HLCDC_LAYER_DMA_IRQ |
|
|
ATMEL_HLCDC_LAYER_DSCR_IRQ |
|
|
ATMEL_HLCDC_LAYER_ADD_IRQ |
|
|
ATMEL_HLCDC_LAYER_DONE_IRQ |
|
|
ATMEL_HLCDC_LAYER_OVR_IRQ) << (8 * i);
|
|
|
|
regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_IER, tmp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void atmel_hlcdc_layer_cleanup(struct drm_device *dev,
|
|
struct atmel_hlcdc_layer *layer)
|
|
{
|
|
const struct atmel_hlcdc_layer_desc *desc = layer->desc;
|
|
struct regmap *regmap = layer->hlcdc->regmap;
|
|
|
|
regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_IDR,
|
|
0xffffffff);
|
|
regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR,
|
|
ATMEL_HLCDC_LAYER_RST);
|
|
|
|
atmel_hlcdc_layer_dma_cleanup(dev, layer);
|
|
drm_flip_work_cleanup(&layer->gc);
|
|
}
|