312 lines
8.3 KiB
C
312 lines
8.3 KiB
C
/*
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* mrst.c: Intel Moorestown platform specific setup code
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*
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* (C) Copyright 2008 Intel Corporation
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* Author: Jacob Pan (jacob.jun.pan@intel.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sfi.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <asm/setup.h>
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#include <asm/mpspec_def.h>
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#include <asm/hw_irq.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/mrst.h>
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#include <asm/io.h>
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#include <asm/i8259.h>
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#include <asm/apb_timer.h>
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/*
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* the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
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* cmdline option x86_mrst_timer can be used to override the configuration
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* to prefer one or the other.
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* at runtime, there are basically three timer configurations:
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* 1. per cpu apbt clock only
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* 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
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* 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
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*
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* by default (without cmdline option), platform code first detects cpu type
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* to see if we are on lincroft or penwell, then set up both lapic or apbt
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* clocks accordingly.
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* i.e. by default, medfield uses configuration #2, moorestown uses #1.
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* config #3 is supported but not recommended on medfield.
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*
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* rating and feature summary:
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* lapic (with C3STOP) --------- 100
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* apbt (always-on) ------------ 110
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* lapic (always-on,ARAT) ------ 150
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*/
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__cpuinitdata enum mrst_timer_options mrst_timer_options;
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static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
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static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
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enum mrst_cpu_type __mrst_cpu_chip;
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EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
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int sfi_mtimer_num;
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struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
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EXPORT_SYMBOL_GPL(sfi_mrtc_array);
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int sfi_mrtc_num;
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static inline void assign_to_mp_irq(struct mpc_intsrc *m,
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struct mpc_intsrc *mp_irq)
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{
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memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
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}
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static inline int mp_irq_cmp(struct mpc_intsrc *mp_irq,
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struct mpc_intsrc *m)
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{
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return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
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}
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static void save_mp_irq(struct mpc_intsrc *m)
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{
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int i;
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for (i = 0; i < mp_irq_entries; i++) {
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if (!mp_irq_cmp(&mp_irqs[i], m))
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return;
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}
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assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
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if (++mp_irq_entries == MAX_IRQ_SOURCES)
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panic("Max # of irq sources exceeded!!\n");
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}
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/* parse all the mtimer info to a static mtimer array */
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static int __init sfi_parse_mtmr(struct sfi_table_header *table)
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{
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struct sfi_table_simple *sb;
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struct sfi_timer_table_entry *pentry;
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struct mpc_intsrc mp_irq;
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int totallen;
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sb = (struct sfi_table_simple *)table;
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if (!sfi_mtimer_num) {
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sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
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struct sfi_timer_table_entry);
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pentry = (struct sfi_timer_table_entry *) sb->pentry;
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totallen = sfi_mtimer_num * sizeof(*pentry);
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memcpy(sfi_mtimer_array, pentry, totallen);
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}
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printk(KERN_INFO "SFI: MTIMER info (num = %d):\n", sfi_mtimer_num);
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pentry = sfi_mtimer_array;
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for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
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printk(KERN_INFO "timer[%d]: paddr = 0x%08x, freq = %dHz,"
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" irq = %d\n", totallen, (u32)pentry->phys_addr,
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pentry->freq_hz, pentry->irq);
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if (!pentry->irq)
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continue;
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mp_irq.type = MP_IOAPIC;
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mp_irq.irqtype = mp_INT;
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/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
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mp_irq.irqflag = 5;
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mp_irq.srcbus = 0;
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mp_irq.srcbusirq = pentry->irq; /* IRQ */
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mp_irq.dstapic = MP_APIC_ALL;
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mp_irq.dstirq = pentry->irq;
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save_mp_irq(&mp_irq);
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}
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return 0;
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}
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struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
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{
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int i;
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if (hint < sfi_mtimer_num) {
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if (!sfi_mtimer_usage[hint]) {
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pr_debug("hint taken for timer %d irq %d\n",\
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hint, sfi_mtimer_array[hint].irq);
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sfi_mtimer_usage[hint] = 1;
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return &sfi_mtimer_array[hint];
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}
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}
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/* take the first timer available */
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for (i = 0; i < sfi_mtimer_num;) {
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if (!sfi_mtimer_usage[i]) {
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sfi_mtimer_usage[i] = 1;
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return &sfi_mtimer_array[i];
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}
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i++;
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}
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return NULL;
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}
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void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
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{
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int i;
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for (i = 0; i < sfi_mtimer_num;) {
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if (mtmr->irq == sfi_mtimer_array[i].irq) {
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sfi_mtimer_usage[i] = 0;
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return;
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}
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i++;
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}
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}
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/* parse all the mrtc info to a global mrtc array */
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int __init sfi_parse_mrtc(struct sfi_table_header *table)
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{
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struct sfi_table_simple *sb;
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struct sfi_rtc_table_entry *pentry;
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struct mpc_intsrc mp_irq;
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int totallen;
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sb = (struct sfi_table_simple *)table;
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if (!sfi_mrtc_num) {
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sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
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struct sfi_rtc_table_entry);
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pentry = (struct sfi_rtc_table_entry *)sb->pentry;
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totallen = sfi_mrtc_num * sizeof(*pentry);
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memcpy(sfi_mrtc_array, pentry, totallen);
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}
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printk(KERN_INFO "SFI: RTC info (num = %d):\n", sfi_mrtc_num);
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pentry = sfi_mrtc_array;
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for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
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printk(KERN_INFO "RTC[%d]: paddr = 0x%08x, irq = %d\n",
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totallen, (u32)pentry->phys_addr, pentry->irq);
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mp_irq.type = MP_IOAPIC;
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mp_irq.irqtype = mp_INT;
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mp_irq.irqflag = 0;
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mp_irq.srcbus = 0;
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mp_irq.srcbusirq = pentry->irq; /* IRQ */
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mp_irq.dstapic = MP_APIC_ALL;
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mp_irq.dstirq = pentry->irq;
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save_mp_irq(&mp_irq);
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}
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return 0;
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}
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static unsigned long __init mrst_calibrate_tsc(void)
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{
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unsigned long flags, fast_calibrate;
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local_irq_save(flags);
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fast_calibrate = apbt_quick_calibrate();
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local_irq_restore(flags);
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if (fast_calibrate)
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return fast_calibrate;
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return 0;
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}
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void __init mrst_time_init(void)
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{
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switch (mrst_timer_options) {
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case MRST_TIMER_APBT_ONLY:
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break;
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case MRST_TIMER_LAPIC_APBT:
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x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
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x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
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break;
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default:
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if (!boot_cpu_has(X86_FEATURE_ARAT))
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break;
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x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
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x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
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return;
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}
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/* we need at least one APB timer */
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sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
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pre_init_apic_IRQ0();
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apbt_time_init();
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}
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void __init mrst_rtc_init(void)
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{
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sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
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}
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void __cpuinit mrst_arch_setup(void)
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{
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if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
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__mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
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else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
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__mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
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else {
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pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
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boot_cpu_data.x86, boot_cpu_data.x86_model);
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__mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
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}
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pr_debug("Moorestown CPU %s identified\n",
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(__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
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"Lincroft" : "Penwell");
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}
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/* MID systems don't have i8042 controller */
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static int mrst_i8042_detect(void)
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{
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return 0;
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}
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/*
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* Moorestown specific x86_init function overrides and early setup
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* calls.
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*/
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void __init x86_mrst_early_setup(void)
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{
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x86_init.resources.probe_roms = x86_init_noop;
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x86_init.resources.reserve_resources = x86_init_noop;
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x86_init.timers.timer_init = mrst_time_init;
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x86_init.timers.setup_percpu_clockev = x86_init_noop;
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x86_init.irqs.pre_vector_init = x86_init_noop;
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x86_init.oem.arch_setup = mrst_arch_setup;
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x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
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x86_platform.calibrate_tsc = mrst_calibrate_tsc;
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x86_platform.i8042_detect = mrst_i8042_detect;
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x86_init.pci.init = pci_mrst_init;
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x86_init.pci.fixup_irqs = x86_init_noop;
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legacy_pic = &null_legacy_pic;
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/* Avoid searching for BIOS MP tables */
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x86_init.mpparse.find_smp_config = x86_init_noop;
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x86_init.mpparse.get_smp_config = x86_init_uint_noop;
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}
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/*
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* if user does not want to use per CPU apb timer, just give it a lower rating
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* than local apic timer and skip the late per cpu timer init.
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*/
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static inline int __init setup_x86_mrst_timer(char *arg)
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{
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if (!arg)
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return -EINVAL;
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if (strcmp("apbt_only", arg) == 0)
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mrst_timer_options = MRST_TIMER_APBT_ONLY;
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else if (strcmp("lapic_and_apbt", arg) == 0)
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mrst_timer_options = MRST_TIMER_LAPIC_APBT;
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else {
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pr_warning("X86 MRST timer option %s not recognised"
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" use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
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arg);
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return -EINVAL;
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}
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return 0;
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}
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__setup("x86_mrst_timer=", setup_x86_mrst_timer);
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