536 lines
14 KiB
C
536 lines
14 KiB
C
#ifndef __ASM_ARM_SYSTEM_H
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#define __ASM_ARM_SYSTEM_H
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#ifdef __KERNEL__
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#define CPU_ARCH_UNKNOWN 0
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#define CPU_ARCH_ARMv3 1
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#define CPU_ARCH_ARMv4 2
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#define CPU_ARCH_ARMv4T 3
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#define CPU_ARCH_ARMv5 4
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#define CPU_ARCH_ARMv5T 5
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#define CPU_ARCH_ARMv5TE 6
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#define CPU_ARCH_ARMv5TEJ 7
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#define CPU_ARCH_ARMv6 8
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#define CPU_ARCH_ARMv7 9
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define CR_TRE (1 << 28) /* TEX remap enable */
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#define CR_AFE (1 << 29) /* Access flag enable */
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#define CR_TE (1 << 30) /* Thumb exception enable */
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/*
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* This is used to ensure the compiler did actually allocate the register we
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* asked it for some inline assembly sequences. Apparently we can't trust
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* the compiler from one version to another so a bit of paranoia won't hurt.
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* This string is meant to be concatenated with the inline asm string and
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* will cause compilation to stop on mismatch.
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* (for details, see gcc PR 15089)
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*/
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#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#include <linux/linkage.h>
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#include <linux/irqflags.h>
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#include <asm/outercache.h>
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struct thread_info;
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struct task_struct;
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/* information about the system we're running on */
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extern unsigned int system_rev;
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extern unsigned int system_serial_low;
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extern unsigned int system_serial_high;
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extern unsigned int mem_fclk_21285;
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struct pt_regs;
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void die(const char *msg, struct pt_regs *regs, int err);
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struct siginfo;
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void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
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unsigned long err, unsigned long trap);
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void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
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struct pt_regs *),
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int sig, int code, const char *name);
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void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
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struct pt_regs *),
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int sig, int code, const char *name);
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#define xchg(ptr,x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
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struct mm_struct;
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extern void show_pte(struct mm_struct *mm, unsigned long addr);
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extern void __show_regs(struct pt_regs *);
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extern int __pure cpu_architecture(void);
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extern void cpu_init(void);
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void arm_machine_restart(char mode, const char *cmd);
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extern void (*arm_pm_restart)(char str, const char *cmd);
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#define UDBG_UNDEFINED (1 << 0)
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#define UDBG_SYSCALL (1 << 1)
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#define UDBG_BADABORT (1 << 2)
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#define UDBG_SEGV (1 << 3)
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#define UDBG_BUS (1 << 4)
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extern unsigned int user_debug;
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#if __LINUX_ARM_ARCH__ >= 4
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#define vectors_high() (cr_alignment & CR_V)
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#else
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#define vectors_high() (0)
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#endif
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#if __LINUX_ARM_ARCH__ >= 7 || \
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(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
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#define sev() __asm__ __volatile__ ("sev" : : : "memory")
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#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
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#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
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#endif
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#if __LINUX_ARM_ARCH__ >= 7
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#define isb() __asm__ __volatile__ ("isb" : : : "memory")
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#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
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#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
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#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
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#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
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: : "r" (0) : "memory")
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#elif defined(CONFIG_CPU_FA526)
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#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
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: : "r" (0) : "memory")
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#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb() __asm__ __volatile__ ("" : : : "memory")
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#else
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#define isb() __asm__ __volatile__ ("" : : : "memory")
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#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
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: : "r" (0) : "memory")
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#define dmb() __asm__ __volatile__ ("" : : : "memory")
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#endif
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#ifdef CONFIG_ARCH_HAS_BARRIERS
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#include <mach/barriers.h>
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#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
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#define mb() do { dsb(); outer_sync(); } while (0)
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#define rmb() dsb()
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#define wmb() mb()
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#else
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#include <asm/memory.h>
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#define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
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#define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
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#define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
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#endif
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#ifndef CONFIG_SMP
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#else
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#define smp_mb() dmb()
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#define smp_rmb() dmb()
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#define smp_wmb() dmb()
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#endif
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#define read_barrier_depends() do { } while(0)
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#define smp_read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; smp_mb(); } while (0)
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
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extern unsigned long cr_alignment; /* defined in entry-armv.S */
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
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: : "r" (val) : "cc");
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isb();
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}
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#ifndef CONFIG_SMP
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extern void adjust_cr(unsigned long mask, unsigned long set);
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#endif
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#define CPACC_FULL(n) (3 << (n * 2))
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#define CPACC_SVC(n) (1 << (n * 2))
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#define CPACC_DISABLE(n) (0 << (n * 2))
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static inline unsigned int get_copro_access(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
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: "=r" (val) : : "cc");
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return val;
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}
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static inline void set_copro_access(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
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: : "r" (val) : "cc");
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isb();
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}
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/*
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* switch_mm() may do a full cache flush over the context switch,
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* so enable interrupts over the context switch to avoid high
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* latency.
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*/
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#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
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/*
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* switch_to(prev, next) should switch from task `prev' to `next'
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* `prev' will never be the same as `next'. schedule() itself
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* contains the memory barrier to tell GCC not to cache `current'.
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*/
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extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
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#define switch_to(prev,next,last) \
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do { \
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last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
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} while (0)
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#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
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/*
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* On the StrongARM, "swp" is terminally broken since it bypasses the
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* cache totally. This means that the cache becomes inconsistent, and,
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* since we use normal loads/stores as well, this is really bad.
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* Typically, this causes oopsen in filp_close, but could have other,
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* more disastrous effects. There are two work-arounds:
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* 1. Disable interrupts and emulate the atomic swap
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* 2. Clean the cache, perform atomic swap, flush the cache
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*
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* We choose (1) since its the "easiest" to achieve here and is not
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* dependent on the processor type.
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*
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* NOTE that this solution won't work on an SMP system, so explcitly
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* forbid it here.
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*/
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#define swp_is_buggy
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#endif
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
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{
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extern void __bad_xchg(volatile void *, int);
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unsigned long ret;
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#ifdef swp_is_buggy
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unsigned long flags;
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#endif
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#if __LINUX_ARM_ARCH__ >= 6
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unsigned int tmp;
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#endif
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smp_mb();
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switch (size) {
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#if __LINUX_ARM_ARCH__ >= 6
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case 1:
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asm volatile("@ __xchg1\n"
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"1: ldrexb %0, [%3]\n"
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" strexb %1, %2, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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case 4:
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asm volatile("@ __xchg4\n"
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"1: ldrex %0, [%3]\n"
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" strex %1, %2, [%3]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (ret), "=&r" (tmp)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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#elif defined(swp_is_buggy)
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#ifdef CONFIG_SMP
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#error SMP is not supported on this platform
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#endif
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case 1:
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raw_local_irq_save(flags);
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ret = *(volatile unsigned char *)ptr;
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*(volatile unsigned char *)ptr = x;
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raw_local_irq_restore(flags);
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break;
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case 4:
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raw_local_irq_save(flags);
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ret = *(volatile unsigned long *)ptr;
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*(volatile unsigned long *)ptr = x;
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raw_local_irq_restore(flags);
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break;
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#else
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case 1:
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asm volatile("@ __xchg1\n"
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" swpb %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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case 4:
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asm volatile("@ __xchg4\n"
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" swp %0, %1, [%2]"
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: "=&r" (ret)
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: "r" (x), "r" (ptr)
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: "memory", "cc");
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break;
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#endif
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default:
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__bad_xchg(ptr, size), ret = 0;
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break;
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}
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smp_mb();
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return ret;
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}
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extern void disable_hlt(void);
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extern void enable_hlt(void);
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void cpu_idle_wait(void);
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#include <asm-generic/cmpxchg-local.h>
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#if __LINUX_ARM_ARCH__ < 6
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/* min ARCH < ARMv6 */
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#ifdef CONFIG_SMP
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#error "SMP is not supported on this platform"
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#endif
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
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(unsigned long)(n), sizeof(*(ptr))))
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#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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#ifndef CONFIG_SMP
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#include <asm-generic/cmpxchg.h>
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#endif
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#else /* min ARCH >= ARMv6 */
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extern void __bad_cmpxchg(volatile void *ptr, int size);
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/*
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* cmpxchg only support 32-bits operands on ARMv6.
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*/
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long oldval, res;
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switch (size) {
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#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
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case 1:
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do {
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asm volatile("@ __cmpxchg1\n"
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" ldrexb %1, [%2]\n"
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" mov %0, #0\n"
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" teq %1, %3\n"
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" strexbeq %0, %4, [%2]\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "memory", "cc");
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} while (res);
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break;
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case 2:
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do {
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asm volatile("@ __cmpxchg1\n"
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" ldrexh %1, [%2]\n"
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" mov %0, #0\n"
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" teq %1, %3\n"
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" strexheq %0, %4, [%2]\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "memory", "cc");
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} while (res);
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break;
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#endif
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case 4:
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do {
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asm volatile("@ __cmpxchg4\n"
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" ldrex %1, [%2]\n"
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" mov %0, #0\n"
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" teq %1, %3\n"
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" strexeq %0, %4, [%2]\n"
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: "=&r" (res), "=&r" (oldval)
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: "r" (ptr), "Ir" (old), "r" (new)
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: "memory", "cc");
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} while (res);
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break;
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default:
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__bad_cmpxchg(ptr, size);
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oldval = 0;
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}
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return oldval;
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}
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static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
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unsigned long new, int size)
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{
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unsigned long ret;
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smp_mb();
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ret = __cmpxchg(ptr, old, new, size);
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smp_mb();
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return ret;
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}
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#define cmpxchg(ptr,o,n) \
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((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \
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(unsigned long)(o), \
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(unsigned long)(n), \
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sizeof(*(ptr))))
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static inline unsigned long __cmpxchg_local(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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unsigned long ret;
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switch (size) {
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#ifdef CONFIG_CPU_V6 /* min ARCH == ARMv6 */
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case 1:
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case 2:
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ret = __cmpxchg_local_generic(ptr, old, new, size);
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break;
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#endif
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default:
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ret = __cmpxchg(ptr, old, new, size);
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}
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return ret;
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}
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#define cmpxchg_local(ptr,o,n) \
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((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
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(unsigned long)(o), \
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(unsigned long)(n), \
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sizeof(*(ptr))))
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#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
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/*
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* Note : ARMv7-M (currently unsupported by Linux) does not support
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* ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
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* not be allowed to use __cmpxchg64.
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*/
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static inline unsigned long long __cmpxchg64(volatile void *ptr,
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unsigned long long old,
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unsigned long long new)
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{
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register unsigned long long oldval asm("r0");
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register unsigned long long __old asm("r2") = old;
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register unsigned long long __new asm("r4") = new;
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unsigned long res;
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do {
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asm volatile(
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" @ __cmpxchg8\n"
|
|
" ldrexd %1, %H1, [%2]\n"
|
|
" mov %0, #0\n"
|
|
" teq %1, %3\n"
|
|
" teqeq %H1, %H3\n"
|
|
" strexdeq %0, %4, %H4, [%2]\n"
|
|
: "=&r" (res), "=&r" (oldval)
|
|
: "r" (ptr), "Ir" (__old), "r" (__new)
|
|
: "memory", "cc");
|
|
} while (res);
|
|
|
|
return oldval;
|
|
}
|
|
|
|
static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
|
|
unsigned long long old,
|
|
unsigned long long new)
|
|
{
|
|
unsigned long long ret;
|
|
|
|
smp_mb();
|
|
ret = __cmpxchg64(ptr, old, new);
|
|
smp_mb();
|
|
|
|
return ret;
|
|
}
|
|
|
|
#define cmpxchg64(ptr,o,n) \
|
|
((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \
|
|
(unsigned long long)(o), \
|
|
(unsigned long long)(n)))
|
|
|
|
#define cmpxchg64_local(ptr,o,n) \
|
|
((__typeof__(*(ptr)))__cmpxchg64((ptr), \
|
|
(unsigned long long)(o), \
|
|
(unsigned long long)(n)))
|
|
|
|
#else /* min ARCH = ARMv6 */
|
|
|
|
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
|
|
|
|
#endif
|
|
|
|
#endif /* __LINUX_ARM_ARCH__ >= 6 */
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#define arch_align_stack(x) (x)
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif
|