267 lines
7.6 KiB
C
267 lines
7.6 KiB
C
/*
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* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/io.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk/tegra.h>
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#include "clk.h"
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#include "clk-id.h"
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#define PLLX_BASE 0xe0
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#define PLLX_MISC 0xe4
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#define PLLX_MISC2 0x514
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#define PLLX_MISC3 0x518
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#define CCLKG_BURST_POLICY 0x368
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#define CCLKLP_BURST_POLICY 0x370
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#define SCLK_BURST_POLICY 0x028
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#define SYSTEM_CLK_RATE 0x030
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#define SCLK_DIVIDER 0x2c
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static DEFINE_SPINLOCK(sysrate_lock);
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enum tegra_super_gen {
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gen4 = 4,
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gen5,
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};
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struct tegra_super_gen_info {
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enum tegra_super_gen gen;
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const char **sclk_parents;
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const char **cclk_g_parents;
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const char **cclk_lp_parents;
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int num_sclk_parents;
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int num_cclk_g_parents;
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int num_cclk_lp_parents;
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};
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static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
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"pll_p", "pll_p_out2", "unused",
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"clk_32k", "pll_m_out1" };
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static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
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"pll_p", "pll_p_out4", "unused",
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"unused", "pll_x", "unused", "unused",
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"unused", "unused", "unused", "unused",
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"dfllCPU_out" };
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static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
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"pll_p", "pll_p_out4", "unused",
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"unused", "pll_x", "pll_x_out0" };
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const struct tegra_super_gen_info tegra_super_gen_info_gen4 = {
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.gen = gen4,
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.sclk_parents = sclk_parents,
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.cclk_g_parents = cclk_g_parents,
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.cclk_lp_parents = cclk_lp_parents,
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.num_sclk_parents = ARRAY_SIZE(sclk_parents),
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.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents),
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.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents),
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};
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static const char *sclk_parents_gen5[] = { "clk_m", "pll_c_out1", "pll_c4_out3",
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"pll_p", "pll_p_out2", "pll_c4_out1",
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"clk_32k", "pll_c4_out2" };
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static const char *cclk_g_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
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"pll_p", "pll_p_out4", "unused",
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"unused", "pll_x", "unused", "unused",
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"unused", "unused", "unused", "unused",
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"dfllCPU_out" };
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static const char *cclk_lp_parents_gen5[] = { "clk_m", "unused", "clk_32k", "unused",
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"pll_p", "pll_p_out4", "unused",
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"unused", "pll_x", "unused", "unused",
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"unused", "unused", "unused", "unused",
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"dfllCPU_out" };
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const struct tegra_super_gen_info tegra_super_gen_info_gen5 = {
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.gen = gen5,
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.sclk_parents = sclk_parents_gen5,
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.cclk_g_parents = cclk_g_parents_gen5,
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.cclk_lp_parents = cclk_lp_parents_gen5,
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.num_sclk_parents = ARRAY_SIZE(sclk_parents_gen5),
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.num_cclk_g_parents = ARRAY_SIZE(cclk_g_parents_gen5),
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.num_cclk_lp_parents = ARRAY_SIZE(cclk_lp_parents_gen5),
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};
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static void __init tegra_sclk_init(void __iomem *clk_base,
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struct tegra_clk *tegra_clks,
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const struct tegra_super_gen_info *gen_info)
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{
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struct clk *clk;
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struct clk **dt_clk;
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/* SCLK_MUX */
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dt_clk = tegra_lookup_dt_id(tegra_clk_sclk_mux, tegra_clks);
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if (dt_clk) {
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clk = tegra_clk_register_super_mux("sclk_mux",
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gen_info->sclk_parents,
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gen_info->num_sclk_parents,
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CLK_SET_RATE_PARENT,
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clk_base + SCLK_BURST_POLICY,
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0, 4, 0, 0, NULL);
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*dt_clk = clk;
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/* SCLK */
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dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
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if (dt_clk) {
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clk = clk_register_divider(NULL, "sclk", "sclk_mux", 0,
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clk_base + SCLK_DIVIDER, 0, 8,
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0, &sysrate_lock);
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*dt_clk = clk;
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}
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} else {
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/* SCLK */
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dt_clk = tegra_lookup_dt_id(tegra_clk_sclk, tegra_clks);
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if (dt_clk) {
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clk = tegra_clk_register_super_mux("sclk",
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gen_info->sclk_parents,
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gen_info->num_sclk_parents,
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CLK_SET_RATE_PARENT,
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clk_base + SCLK_BURST_POLICY,
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0, 4, 0, 0, NULL);
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*dt_clk = clk;
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}
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}
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/* HCLK */
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dt_clk = tegra_lookup_dt_id(tegra_clk_hclk, tegra_clks);
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if (dt_clk) {
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clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
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clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
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&sysrate_lock);
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clk = clk_register_gate(NULL, "hclk", "hclk_div",
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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clk_base + SYSTEM_CLK_RATE,
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7, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
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*dt_clk = clk;
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}
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/* PCLK */
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dt_clk = tegra_lookup_dt_id(tegra_clk_pclk, tegra_clks);
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if (!dt_clk)
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return;
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clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
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clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
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&sysrate_lock);
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clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
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CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE,
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3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
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*dt_clk = clk;
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}
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void __init tegra_super_clk_init(void __iomem *clk_base,
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void __iomem *pmc_base,
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struct tegra_clk *tegra_clks,
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struct tegra_clk_pll_params *params,
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const struct tegra_super_gen_info *gen_info)
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{
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struct clk *clk;
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struct clk **dt_clk;
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/* CCLKG */
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dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_g, tegra_clks);
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if (dt_clk) {
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if (gen_info->gen == gen5) {
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clk = tegra_clk_register_super_mux("cclk_g",
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gen_info->cclk_g_parents,
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gen_info->num_cclk_g_parents,
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CLK_SET_RATE_PARENT,
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clk_base + CCLKG_BURST_POLICY,
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0, 4, 8, 0, NULL);
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} else {
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clk = tegra_clk_register_super_mux("cclk_g",
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gen_info->cclk_g_parents,
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gen_info->num_cclk_g_parents,
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CLK_SET_RATE_PARENT,
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clk_base + CCLKG_BURST_POLICY,
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0, 4, 0, 0, NULL);
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}
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*dt_clk = clk;
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}
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/* CCLKLP */
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dt_clk = tegra_lookup_dt_id(tegra_clk_cclk_lp, tegra_clks);
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if (dt_clk) {
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if (gen_info->gen == gen5) {
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clk = tegra_clk_register_super_mux("cclk_lp",
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gen_info->cclk_lp_parents,
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gen_info->num_cclk_lp_parents,
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CLK_SET_RATE_PARENT,
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clk_base + CCLKLP_BURST_POLICY,
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0, 4, 8, 0, NULL);
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} else {
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clk = tegra_clk_register_super_mux("cclk_lp",
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gen_info->cclk_lp_parents,
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gen_info->num_cclk_lp_parents,
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CLK_SET_RATE_PARENT,
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clk_base + CCLKLP_BURST_POLICY,
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TEGRA_DIVIDER_2, 4, 8, 9, NULL);
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}
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*dt_clk = clk;
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}
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tegra_sclk_init(clk_base, tegra_clks, gen_info);
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#if defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
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defined(CONFIG_ARCH_TEGRA_210_SOC)
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/* PLLX */
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dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x, tegra_clks);
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if (!dt_clk)
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return;
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clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base,
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pmc_base, CLK_IGNORE_UNUSED, params, NULL);
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*dt_clk = clk;
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/* PLLX_OUT0 */
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dt_clk = tegra_lookup_dt_id(tegra_clk_pll_x_out0, tegra_clks);
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if (!dt_clk)
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return;
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clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
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CLK_SET_RATE_PARENT, 1, 2);
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*dt_clk = clk;
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#endif
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}
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void __init tegra_super_clk_gen4_init(void __iomem *clk_base,
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void __iomem *pmc_base,
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struct tegra_clk *tegra_clks,
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struct tegra_clk_pll_params *params)
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{
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tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
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&tegra_super_gen_info_gen4);
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}
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void __init tegra_super_clk_gen5_init(void __iomem *clk_base,
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void __iomem *pmc_base,
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struct tegra_clk *tegra_clks,
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struct tegra_clk_pll_params *params)
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{
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tegra_super_clk_init(clk_base, pmc_base, tegra_clks, params,
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&tegra_super_gen_info_gen5);
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}
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