122 lines
4.8 KiB
C
122 lines
4.8 KiB
C
/*
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* This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
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* driver for Linux.
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*
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* Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __T4VF_DEFS_H__
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#define __T4VF_DEFS_H__
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#include "../cxgb4/t4_regs.h"
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/*
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* The VF Register Map.
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*
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* The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
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* bus module (PL) and CPU Interface Module (CIM) components are mapped via
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* the Slice to Module Map Table (see below) in the Physical Function Register
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* Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
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* and Offset registers in the PF Register Map. The MBDATA base address is
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* quite constrained as it determines the Mailbox Data addresses for both PFs
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* and VFs, and therefore must fit in both the VF and PF Register Maps without
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* overlapping other registers.
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*/
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#define T4VF_SGE_BASE_ADDR 0x0000
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#define T4VF_MPS_BASE_ADDR 0x0100
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#define T4VF_PL_BASE_ADDR 0x0200
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#define T4VF_MBDATA_BASE_ADDR 0x0240
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#define T4VF_CIM_BASE_ADDR 0x0300
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#define T4VF_REGMAP_START 0x0000
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#define T4VF_REGMAP_SIZE 0x0400
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/*
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* There's no hardware limitation which requires that the addresses of the
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* Mailbox Data in the fixed CIM PF map and the programmable VF map must
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* match. However, it's a useful convention ...
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*/
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#if T4VF_MBDATA_BASE_ADDR != CIM_PF_MAILBOX_DATA
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#error T4VF_MBDATA_BASE_ADDR must match CIM_PF_MAILBOX_DATA!
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#endif
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/*
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* Virtual Function "Slice to Module Map Table" definitions.
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*
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* This table allows us to map subsets of the various module register sets
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* into the T4VF Register Map. Each table entry identifies the index of the
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* module whose registers are being mapped, the offset within the module's
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* register set that the mapping should start at, the limit of the mapping,
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* and the offset within the T4VF Register Map to which the module's registers
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* are being mapped. All addresses and qualtities are in terms of 32-bit
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* words. The "limit" value is also in terms of 32-bit words and is equal to
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* the last address mapped in the T4VF Register Map 1 (i.e. it's a "<="
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* relation rather than a "<").
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*/
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#define T4VF_MOD_MAP(module, index, first, last) \
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T4VF_MOD_MAP_##module##_INDEX = (index), \
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T4VF_MOD_MAP_##module##_FIRST = (first), \
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T4VF_MOD_MAP_##module##_LAST = (last), \
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T4VF_MOD_MAP_##module##_OFFSET = ((first)/4), \
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T4VF_MOD_MAP_##module##_BASE = \
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(T4VF_##module##_BASE_ADDR/4 + (first)/4), \
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T4VF_MOD_MAP_##module##_LIMIT = \
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(T4VF_##module##_BASE_ADDR/4 + (last)/4),
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#define SGE_VF_KDOORBELL 0x0
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#define SGE_VF_GTS 0x4
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#define MPS_VF_CTL 0x0
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#define MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
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#define PL_VF_WHOAMI 0x0
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#define CIM_VF_EXT_MAILBOX_CTRL 0x0
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#define CIM_VF_EXT_MAILBOX_STATUS 0x4
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enum {
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T4VF_MOD_MAP(SGE, 2, SGE_VF_KDOORBELL, SGE_VF_GTS)
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T4VF_MOD_MAP(MPS, 0, MPS_VF_CTL, MPS_VF_STAT_RX_VF_ERR_FRAMES_H)
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T4VF_MOD_MAP(PL, 3, PL_VF_WHOAMI, PL_VF_WHOAMI)
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T4VF_MOD_MAP(CIM, 1, CIM_VF_EXT_MAILBOX_CTRL, CIM_VF_EXT_MAILBOX_STATUS)
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};
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/*
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* There isn't a Slice to Module Map Table entry for the Mailbox Data
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* registers, but it's convenient to use similar names as above. There are 8
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* little-endian 64-bit Mailbox Data registers. Note that the "instances"
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* value below is in terms of 32-bit words which matches the "word" addressing
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* space we use above for the Slice to Module Map Space.
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*/
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#define NUM_CIM_VF_MAILBOX_DATA_INSTANCES 16
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#define T4VF_MBDATA_FIRST 0
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#define T4VF_MBDATA_LAST ((NUM_CIM_VF_MAILBOX_DATA_INSTANCES-1)*4)
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#endif /* __T4T4VF_DEFS_H__ */
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