152 lines
3.6 KiB
C
152 lines
3.6 KiB
C
/*
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* Marvell Armada AP806 System Controller
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*
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* Copyright (C) 2016 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) "ap806-system-controller: " fmt
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#define AP806_SAR_REG 0x400
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#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
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#define AP806_CLK_NUM 4
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static struct clk *ap806_clks[AP806_CLK_NUM];
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static struct clk_onecell_data ap806_clk_data = {
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.clks = ap806_clks,
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.clk_num = AP806_CLK_NUM,
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};
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static int ap806_syscon_clk_probe(struct platform_device *pdev)
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{
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unsigned int freq_mode, cpuclk_freq;
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const char *name, *fixedclk_name;
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struct device_node *np = pdev->dev.of_node;
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struct regmap *regmap;
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u32 reg;
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int ret;
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regmap = syscon_node_to_regmap(np);
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if (IS_ERR(regmap)) {
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dev_err(&pdev->dev, "cannot get regmap\n");
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return PTR_ERR(regmap);
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}
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ret = regmap_read(regmap, AP806_SAR_REG, ®);
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if (ret) {
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dev_err(&pdev->dev, "cannot read from regmap\n");
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return ret;
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}
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freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
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switch (freq_mode) {
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case 0x0 ... 0x5:
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cpuclk_freq = 2000;
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break;
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case 0x6 ... 0xB:
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cpuclk_freq = 1800;
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break;
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case 0xC ... 0x11:
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cpuclk_freq = 1600;
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break;
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case 0x12 ... 0x16:
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cpuclk_freq = 1400;
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break;
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case 0x17 ... 0x19:
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cpuclk_freq = 1300;
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break;
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default:
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dev_err(&pdev->dev, "invalid SAR value\n");
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return -EINVAL;
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}
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/* Convert to hertz */
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cpuclk_freq *= 1000 * 1000;
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/* CPU clocks depend on the Sample At Reset configuration */
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of_property_read_string_index(np, "clock-output-names",
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0, &name);
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ap806_clks[0] = clk_register_fixed_rate(&pdev->dev, name, NULL,
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0, cpuclk_freq);
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if (IS_ERR(ap806_clks[0])) {
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ret = PTR_ERR(ap806_clks[0]);
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goto fail0;
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}
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of_property_read_string_index(np, "clock-output-names",
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1, &name);
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ap806_clks[1] = clk_register_fixed_rate(&pdev->dev, name, NULL, 0,
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cpuclk_freq);
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if (IS_ERR(ap806_clks[1])) {
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ret = PTR_ERR(ap806_clks[1]);
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goto fail1;
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}
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/* Fixed clock is always 1200 Mhz */
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of_property_read_string_index(np, "clock-output-names",
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2, &fixedclk_name);
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ap806_clks[2] = clk_register_fixed_rate(&pdev->dev, fixedclk_name, NULL,
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0, 1200 * 1000 * 1000);
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if (IS_ERR(ap806_clks[2])) {
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ret = PTR_ERR(ap806_clks[2]);
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goto fail2;
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}
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/* MSS Clock is fixed clock divided by 6 */
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of_property_read_string_index(np, "clock-output-names",
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3, &name);
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ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
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0, 1, 6);
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if (IS_ERR(ap806_clks[3])) {
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ret = PTR_ERR(ap806_clks[3]);
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goto fail3;
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}
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ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
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if (ret)
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goto fail_clk_add;
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return 0;
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fail_clk_add:
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clk_unregister_fixed_factor(ap806_clks[3]);
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fail3:
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clk_unregister_fixed_rate(ap806_clks[2]);
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fail2:
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clk_unregister_fixed_rate(ap806_clks[1]);
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fail1:
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clk_unregister_fixed_rate(ap806_clks[0]);
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fail0:
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return ret;
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}
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static const struct of_device_id ap806_syscon_of_match[] = {
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{ .compatible = "marvell,ap806-system-controller", },
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{ }
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};
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static struct platform_driver ap806_syscon_driver = {
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.probe = ap806_syscon_clk_probe,
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.driver = {
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.name = "marvell-ap806-system-controller",
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.of_match_table = ap806_syscon_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(ap806_syscon_driver);
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