205 lines
6.0 KiB
C
205 lines
6.0 KiB
C
/*
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* Low-Level PCI Support for the SH7751
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*
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* Dustin McIntire (dustin@sensoria.com)
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* Derived from arch/i386/kernel/pci-*.c which bore the message:
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* (c) 1999--2000 Martin Mares <mj@ucw.cz>
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*
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* Ported to the new API by Paul Mundt <lethal@linux-sh.org>
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* With cleanup by Paul van Gool <pvangool@mimotech.com>
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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*/
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#undef DEBUG
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include "pci-sh4.h"
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#include <asm/addrspace.h>
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#include <asm/io.h>
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/*
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* Initialization. Try all known PCI access methods. Note that we support
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* using both PCI BIOS and direct access: in such cases, we use I/O ports
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* to access config space.
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*
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* Note that the platform specific initialization (BSC registers, and memory
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* space mapping) will be called via the platform defined function
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* pcibios_init_platform().
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*/
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static int __init sh7751_pci_init(void)
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{
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unsigned int id;
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int ret;
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pr_debug("PCI: Starting intialization.\n");
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/* check for SH7751/SH7751R hardware */
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id = pci_read_reg(SH7751_PCICONF0);
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if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
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id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
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pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
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return -ENODEV;
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}
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if ((ret = sh4_pci_check_direct()) != 0)
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return ret;
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return pcibios_init_platform();
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}
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subsys_initcall(sh7751_pci_init);
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static int __init __area_sdram_check(unsigned int area)
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{
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u32 word;
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word = ctrl_inl(SH7751_BCR1);
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/* check BCR for SDRAM in area */
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if (((word >> area) & 1) == 0) {
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printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
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area, word);
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return 0;
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}
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pci_write_reg(word, SH4_PCIBCR1);
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word = (u16)ctrl_inw(SH7751_BCR2);
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/* check BCR2 for 32bit SDRAM interface*/
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if (((word >> (area << 1)) & 0x3) != 0x3) {
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printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
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area, word);
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return 0;
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}
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pci_write_reg(word, SH4_PCIBCR2);
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return 1;
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}
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int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
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{
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u32 reg;
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u32 word;
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/* Set the BCR's to enable PCI access */
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reg = ctrl_inl(SH7751_BCR1);
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reg |= 0x80000;
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ctrl_outl(reg, SH7751_BCR1);
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/* Turn the clocks back on (not done in reset)*/
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pci_write_reg(0, SH4_PCICLKR);
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/* Clear Powerdown IRQ's (not done in reset) */
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word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
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pci_write_reg(word, SH4_PCIPINT);
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/*
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* This code is unused for some boards as it is done in the
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* bootloader and doing it here means the MAC addresses loaded
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* by the bootloader get lost.
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*/
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if (!(map->flags & SH4_PCIC_NO_RESET)) {
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/* toggle PCI reset pin */
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word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
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pci_write_reg(word, SH4_PCICR);
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/* Wait for a long time... not 1 sec. but long enough */
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mdelay(100);
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word = SH4_PCICR_PREFIX;
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pci_write_reg(word, SH4_PCICR);
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}
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/* set the command/status bits to:
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* Wait Cycle Control + Parity Enable + Bus Master +
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* Mem space enable
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*/
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word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
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SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
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pci_write_reg(word, SH7751_PCICONF1);
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/* define this host as the host bridge */
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word = PCI_BASE_CLASS_BRIDGE << 24;
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pci_write_reg(word, SH7751_PCICONF2);
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/* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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* Window0 = map->window0.size @ non-cached area base = SDRAM
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* Window1 = map->window1.size @ cached area base = SDRAM
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*/
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word = map->window0.size - 1;
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pci_write_reg(word, SH4_PCILSR0);
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word = map->window1.size - 1;
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pci_write_reg(word, SH4_PCILSR1);
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/* Set the values on window 0 PCI config registers */
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word = P2SEGADDR(map->window0.base);
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pci_write_reg(word, SH4_PCILAR0);
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pci_write_reg(word, SH7751_PCICONF5);
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/* Set the values on window 1 PCI config registers */
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word = PHYSADDR(map->window1.base);
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pci_write_reg(word, SH4_PCILAR1);
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pci_write_reg(word, SH7751_PCICONF6);
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/* Set the local 16MB PCI memory space window to
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* the lowest PCI mapped address
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*/
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word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK;
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pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
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pci_write_reg(word , SH4_PCIMBR);
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/* Map IO space into PCI IO window
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* The IO window is 64K-PCIBIOS_MIN_IO in size
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* IO addresses will be translated to the
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* PCI IO window base address
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*/
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pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
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PCIBIOS_MIN_IO, (64 << 10),
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SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO);
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/* Make sure the MSB's of IO window are set to access PCI space
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* correctly */
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word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK;
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pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
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pci_write_reg(word, SH4_PCIIOBR);
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/* Set PCI WCRx, BCRx's, copy from BSC locations */
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/* check BCR for SDRAM in specified area */
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switch (map->window0.base) {
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case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break;
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case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break;
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case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break;
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case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break;
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case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break;
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case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break;
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case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break;
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}
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if (!word)
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return 0;
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/* configure the wait control registers */
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word = ctrl_inl(SH7751_WCR1);
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pci_write_reg(word, SH4_PCIWCR1);
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word = ctrl_inl(SH7751_WCR2);
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pci_write_reg(word, SH4_PCIWCR2);
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word = ctrl_inl(SH7751_WCR3);
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pci_write_reg(word, SH4_PCIWCR3);
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word = ctrl_inl(SH7751_MCR);
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pci_write_reg(word, SH4_PCIMCR);
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/* NOTE: I'm ignoring the PCI error IRQs for now..
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* TODO: add support for the internal error interrupts and
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* DMA interrupts...
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*/
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pci_fixup_pcic();
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/* SH7751 init done, set central function init complete */
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/* use round robin mode to stop a device starving/overruning */
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word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
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pci_write_reg(word, SH4_PCICR);
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return 1;
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}
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