391 lines
16 KiB
ReStructuredText
391 lines
16 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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=========================
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Introduction to LoongArch
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=========================
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LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
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currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
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version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
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(PLVs) defined in LoongArch: PLV0~PLV3, from high to low. Kernel runs at PLV0
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while applications run at PLV3. This document introduces the registers, basic
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instruction set, virtual memory and some other topics of LoongArch.
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Registers
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=========
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LoongArch registers include general purpose registers (GPRs), floating point
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registers (FPRs), vector registers (VRs) and control status registers (CSRs)
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used in privileged mode (PLV0).
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GPRs
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----
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LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
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and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
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are not architecturally special. (Except ``$r1``, which is hard-wired as the
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link register of the BL instruction.)
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The kernel uses a variant of the LoongArch register convention, as described in
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the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
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================= =============== =================== ============
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Name Alias Usage Preserved
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across calls
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================= =============== =================== ============
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``$r0`` ``$zero`` Constant zero Unused
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``$r1`` ``$ra`` Return address No
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``$r2`` ``$tp`` TLS/Thread pointer Unused
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``$r3`` ``$sp`` Stack pointer Yes
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``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
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``$r4``-``$r5`` ``$v0``-``$v1`` Return value No
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``$r12``-``$r20`` ``$t0``-``$t8`` Temp registers No
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``$r21`` ``$u0`` Percpu base address Unused
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``$r22`` ``$fp`` Frame pointer Yes
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``$r23``-``$r31`` ``$s0``-``$s8`` Static registers Yes
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================= =============== =================== ============
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.. Note::
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The register ``$r21`` is reserved in the ELF psABI, but used by the Linux
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kernel for storing the percpu base address. It normally has no ABI name,
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but is called ``$u0`` in the kernel. You may also see ``$v0`` or ``$v1``
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in some old code,however they are deprecated aliases of ``$a0`` and ``$a1``
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respectively.
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FPRs
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----
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LoongArch has 32 FPRs ( ``$f0`` ~ ``$f31`` ) when FPU is present. Each one is
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64-bit wide on the LA64 cores.
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The floating-point register convention is the same as described in the
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LoongArch ELF psABI spec:
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================= ================== =================== ============
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Name Alias Usage Preserved
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across calls
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================= ================== =================== ============
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``$f0``-``$f7`` ``$fa0``-``$fa7`` Argument registers No
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``$f0``-``$f1`` ``$fv0``-``$fv1`` Return value No
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``$f8``-``$f23`` ``$ft0``-``$ft15`` Temp registers No
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``$f24``-``$f31`` ``$fs0``-``$fs7`` Static registers Yes
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================= ================== =================== ============
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.. Note::
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You may see ``$fv0`` or ``$fv1`` in some old code, however they are
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deprecated aliases of ``$fa0`` and ``$fa1`` respectively.
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VRs
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----
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There are currently 2 vector extensions to LoongArch:
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- LSX (Loongson SIMD eXtension) with 128-bit vectors,
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- LASX (Loongson Advanced SIMD eXtension) with 256-bit vectors.
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LSX brings ``$v0`` ~ ``$v31`` while LASX brings ``$x0`` ~ ``$x31`` as the vector
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registers.
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The VRs overlap with FPRs: for example, on a core implementing LSX and LASX,
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the lower 128 bits of ``$x0`` is shared with ``$v0``, and the lower 64 bits of
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``$v0`` is shared with ``$f0``; same with all other VRs.
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CSRs
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----
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CSRs can only be accessed from privileged mode (PLV0):
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================= ===================================== ==============
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Address Full Name Abbrev Name
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================= ===================================== ==============
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0x0 Current Mode Information CRMD
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0x1 Pre-exception Mode Information PRMD
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0x2 Extension Unit Enable EUEN
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0x3 Miscellaneous Control MISC
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0x4 Exception Configuration ECFG
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0x5 Exception Status ESTAT
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0x6 Exception Return Address ERA
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0x7 Bad (Faulting) Virtual Address BADV
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0x8 Bad (Faulting) Instruction Word BADI
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0xC Exception Entrypoint Address EENTRY
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0x10 TLB Index TLBIDX
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0x11 TLB Entry High-order Bits TLBEHI
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0x12 TLB Entry Low-order Bits 0 TLBELO0
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0x13 TLB Entry Low-order Bits 1 TLBELO1
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0x18 Address Space Identifier ASID
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0x19 Page Global Directory Address for PGDL
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Lower-half Address Space
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0x1A Page Global Directory Address for PGDH
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Higher-half Address Space
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0x1B Page Global Directory Address PGD
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0x1C Page Walk Control for Lower- PWCL
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half Address Space
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0x1D Page Walk Control for Higher- PWCH
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half Address Space
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0x1E STLB Page Size STLBPS
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0x1F Reduced Virtual Address Configuration RVACFG
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0x20 CPU Identifier CPUID
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0x21 Privileged Resource Configuration 1 PRCFG1
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0x22 Privileged Resource Configuration 2 PRCFG2
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0x23 Privileged Resource Configuration 3 PRCFG3
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0x30+n (0≤n≤15) Saved Data register SAVEn
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0x40 Timer Identifier TID
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0x41 Timer Configuration TCFG
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0x42 Timer Value TVAL
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0x43 Compensation of Timer Count CNTC
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0x44 Timer Interrupt Clearing TICLR
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0x60 LLBit Control LLBCTL
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0x80 Implementation-specific Control 1 IMPCTL1
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0x81 Implementation-specific Control 2 IMPCTL2
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0x88 TLB Refill Exception Entrypoint TLBRENTRY
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Address
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0x89 TLB Refill Exception BAD (Faulting) TLBRBADV
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Virtual Address
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0x8A TLB Refill Exception Return Address TLBRERA
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0x8B TLB Refill Exception Saved Data TLBRSAVE
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Register
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0x8C TLB Refill Exception Entry Low-order TLBRELO0
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Bits 0
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0x8D TLB Refill Exception Entry Low-order TLBRELO1
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Bits 1
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0x8E TLB Refill Exception Entry High-order TLBEHI
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Bits
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0x8F TLB Refill Exception Pre-exception TLBRPRMD
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Mode Information
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0x90 Machine Error Control MERRCTL
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0x91 Machine Error Information 1 MERRINFO1
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0x92 Machine Error Information 2 MERRINFO2
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0x93 Machine Error Exception Entrypoint MERRENTRY
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Address
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0x94 Machine Error Exception Return MERRERA
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Address
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0x95 Machine Error Exception Saved Data MERRSAVE
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Register
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0x98 Cache TAGs CTAG
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0x180+n (0≤n≤3) Direct Mapping Configuration Window n DMWn
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0x200+2n (0≤n≤31) Performance Monitor Configuration n PMCFGn
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0x201+2n (0≤n≤31) Performance Monitor Overall Counter n PMCNTn
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0x300 Memory Load/Store WatchPoint MWPC
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Overall Control
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0x301 Memory Load/Store WatchPoint MWPS
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Overall Status
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0x310+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG1
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Configuration 1
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0x311+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG2
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Configuration 2
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0x312+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG3
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Configuration 3
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0x313+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG4
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Configuration 4
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0x380 Instruction Fetch WatchPoint FWPC
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Overall Control
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0x381 Instruction Fetch WatchPoint FWPS
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Overall Status
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0x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1
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Configuration 1
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0x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2
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Configuration 2
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0x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3
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Configuration 3
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0x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4
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Configuration 4
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0x500 Debug Register DBG
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0x501 Debug Exception Return Address DERA
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0x502 Debug Exception Saved Data Register DSAVE
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================= ===================================== ==============
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ERA, TLBRERA, MERRERA and DERA are sometimes also known as EPC, TLBREPC, MERREPC
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and DEPC respectively.
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Basic Instruction Set
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=====================
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Instruction formats
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-------------------
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LoongArch instructions are 32 bits wide, belonging to 9 basic instruction
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formats (and variants of them):
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=========== ==========================
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Format name Composition
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=========== ==========================
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2R Opcode + Rj + Rd
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3R Opcode + Rk + Rj + Rd
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4R Opcode + Ra + Rk + Rj + Rd
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2RI8 Opcode + I8 + Rj + Rd
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2RI12 Opcode + I12 + Rj + Rd
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2RI14 Opcode + I14 + Rj + Rd
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2RI16 Opcode + I16 + Rj + Rd
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1RI21 Opcode + I21L + Rj + I21H
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I26 Opcode + I26L + I26H
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=========== ==========================
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Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for
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"additional") are the source register operands. I8/I12/I14/I16/I21/I26 are
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immediate operands of respective width. The longer I21 and I26 are stored
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in separate higher and lower parts in the instruction word, denoted by the "L"
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and "H" suffixes.
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List of Instructions
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--------------------
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For brevity, only instruction names (mnemonics) are listed here; please see the
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:ref:`References <loongarch-references>` for details.
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1. Arithmetic Instructions::
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ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
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SLT SLTU SLTI SLTUI
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AND OR NOR XOR ANDN ORN ANDI ORI XORI
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MUL.W MULH.W MULH.WU DIV.W DIV.WU MOD.W MOD.WU
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MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
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PCADDI PCADDU12I PCADDU18I
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LU12I.W LU32I.D LU52I.D ADDU16I.D
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2. Bit-shift Instructions::
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SLL.W SRL.W SRA.W ROTR.W SLLI.W SRLI.W SRAI.W ROTRI.W
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SLL.D SRL.D SRA.D ROTR.D SLLI.D SRLI.D SRAI.D ROTRI.D
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3. Bit-manipulation Instructions::
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EXT.W.B EXT.W.H CLO.W CLO.D SLZ.W CLZ.D CTO.W CTO.D CTZ.W CTZ.D
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BYTEPICK.W BYTEPICK.D BSTRINS.W BSTRINS.D BSTRPICK.W BSTRPICK.D
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REVB.2H REVB.4H REVB.2W REVB.D REVH.2W REVH.D BITREV.4B BITREV.8B BITREV.W BITREV.D
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MASKEQZ MASKNEZ
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4. Branch Instructions::
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BEQ BNE BLT BGE BLTU BGEU BEQZ BNEZ B BL JIRL
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5. Load/Store Instructions::
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LD.B LD.BU LD.H LD.HU LD.W LD.WU LD.D ST.B ST.H ST.W ST.D
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LDX.B LDX.BU LDX.H LDX.HU LDX.W LDX.WU LDX.D STX.B STX.H STX.W STX.D
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LDPTR.W LDPTR.D STPTR.W STPTR.D
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PRELD PRELDX
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6. Atomic Operation Instructions::
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LL.W SC.W LL.D SC.D
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AMSWAP.W AMSWAP.D AMADD.W AMADD.D AMAND.W AMAND.D AMOR.W AMOR.D AMXOR.W AMXOR.D
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AMMAX.W AMMAX.D AMMIN.W AMMIN.D
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7. Barrier Instructions::
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IBAR DBAR
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8. Special Instructions::
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SYSCALL BREAK CPUCFG NOP IDLE ERTN(ERET) DBCL(DBGCALL) RDTIMEL.W RDTIMEH.W RDTIME.D
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ASRTLE.D ASRTGT.D
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9. Privileged Instructions::
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CSRRD CSRWR CSRXCHG
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IOCSRRD.B IOCSRRD.H IOCSRRD.W IOCSRRD.D IOCSRWR.B IOCSRWR.H IOCSRWR.W IOCSRWR.D
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CACOP TLBP(TLBSRCH) TLBRD TLBWR TLBFILL TLBCLR TLBFLUSH INVTLB LDDIR LDPTE
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Virtual Memory
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==============
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LoongArch supports direct-mapped virtual memory and page-mapped virtual memory.
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Direct-mapped virtual memory is configured by CSR.DMWn (n=0~3), it has a simple
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relationship between virtual address (VA) and physical address (PA)::
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VA = PA + FixedOffset
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Page-mapped virtual memory has arbitrary relationship between VA and PA, which
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is recorded in TLB and page tables. LoongArch's TLB includes a fully-associative
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MTLB (Multiple Page Size TLB) and set-associative STLB (Single Page Size TLB).
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By default, the whole virtual address space of LA32 is configured like this:
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============ =========================== =============================
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Name Address Range Attributes
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============ =========================== =============================
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``UVRANGE`` ``0x00000000 - 0x7FFFFFFF`` Page-mapped, Cached, PLV0~3
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``KPRANGE0`` ``0x80000000 - 0x9FFFFFFF`` Direct-mapped, Uncached, PLV0
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``KPRANGE1`` ``0xA0000000 - 0xBFFFFFFF`` Direct-mapped, Cached, PLV0
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``KVRANGE`` ``0xC0000000 - 0xFFFFFFFF`` Page-mapped, Cached, PLV0
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============ =========================== =============================
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User mode (PLV3) can only access UVRANGE. For direct-mapped KPRANGE0 and
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KPRANGE1, PA is equal to VA with bit30~31 cleared. For example, the uncached
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direct-mapped VA of 0x00001000 is 0x80001000, and the cached direct-mapped
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VA of 0x00001000 is 0xA0001000.
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By default, the whole virtual address space of LA64 is configured like this:
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============ ====================== ======================================
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Name Address Range Attributes
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============ ====================== ======================================
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``XUVRANGE`` ``0x0000000000000000 - Page-mapped, Cached, PLV0~3
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0x3FFFFFFFFFFFFFFF``
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``XSPRANGE`` ``0x4000000000000000 - Direct-mapped, Cached / Uncached, PLV0
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0x7FFFFFFFFFFFFFFF``
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``XKPRANGE`` ``0x8000000000000000 - Direct-mapped, Cached / Uncached, PLV0
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0xBFFFFFFFFFFFFFFF``
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``XKVRANGE`` ``0xC000000000000000 - Page-mapped, Cached, PLV0
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0xFFFFFFFFFFFFFFFF``
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============ ====================== ======================================
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User mode (PLV3) can only access XUVRANGE. For direct-mapped XSPRANGE and
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XKPRANGE, PA is equal to VA with bits 60~63 cleared, and the cache attribute
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is configured by bits 60~61 in VA: 0 is for strongly-ordered uncached, 1 is
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for coherent cached, and 2 is for weakly-ordered uncached.
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Currently we only use XKPRANGE for direct mapping and XSPRANGE is reserved.
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To put this in action: the strongly-ordered uncached direct-mapped VA (in
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XKPRANGE) of 0x00000000_00001000 is 0x80000000_00001000, the coherent cached
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direct-mapped VA (in XKPRANGE) of 0x00000000_00001000 is 0x90000000_00001000,
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and the weakly-ordered uncached direct-mapped VA (in XKPRANGE) of 0x00000000
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_00001000 is 0xA0000000_00001000.
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Relationship of Loongson and LoongArch
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======================================
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LoongArch is a RISC ISA which is different from any other existing ones, while
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Loongson is a family of processors. Loongson includes 3 series: Loongson-1 is
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the 32-bit processor series, Loongson-2 is the low-end 64-bit processor series,
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and Loongson-3 is the high-end 64-bit processor series. Old Loongson is based on
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MIPS, while New Loongson is based on LoongArch. Take Loongson-3 as an example:
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Loongson-3A1000/3B1500/3A2000/3A3000/3A4000 are MIPS-compatible, while Loongson-
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3A5000 (and future revisions) are all based on LoongArch.
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.. _loongarch-references:
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References
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==========
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Official web site of Loongson Technology Corp. Ltd.:
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http://www.loongson.cn/
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Developer web site of Loongson and LoongArch (Software and Documentation):
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http://www.loongnix.cn/
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https://github.com/loongson/
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https://loongson.github.io/LoongArch-Documentation/
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Documentation of LoongArch ISA:
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.00-CN.pdf (in Chinese)
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.00-EN.pdf (in English)
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Documentation of LoongArch ELF psABI:
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v1.00-CN.pdf (in Chinese)
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https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-ELF-ABI-v1.00-EN.pdf (in English)
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Linux kernel repository of Loongson and LoongArch:
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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git
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